公开(公告)号：US10325666B2

公开(公告)日：2019-06-18

申请号：US16218398

申请日：2018-12-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C7/00 ,  G11C16/30 ,  G11C16/08 ,  G11C16/04 ,  G11C16/14 ,  H01L27/11521 ,  G11C16/26 ,  G11C5/14 ,  G11C16/10 ,  G11C8/08 ,  G11C16/16

Abstract: During a program, read, or erase operation of one or more non-volatile flash memory cells in an array of non-volatile flash memory cells, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected non-volatile flash memory cells. The negative voltage is generated by a negative high voltage level shifter using one of several embodiments disclosed herein.

公开(公告)号：US20190172543A1

公开(公告)日：2019-06-06

申请号：US16271673

申请日：2019-02-08

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Xinjie Guo ,  Farnood Merrikh Bayat ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari

IPC: G11C16/34 ,  H01L27/11524 ,  H01L29/788 ,  G11C16/04 ,  G11C8/14 ,  H01L27/11521 ,  G11C16/26 ,  G11C16/14 ,  G11C16/10 ,  H01L27/11558 ,  G11C7/18

CPC classification number: G11C16/3431 ,  G11C7/18 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11558 ,  H01L29/7881

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

公开(公告)号：US20190088329A1

公开(公告)日：2019-03-21

申请号：US16107282

申请日：2018-08-21

Applicant: Silicon Storage Technology, Inc

Inventor： Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  H01L27/11521 ,  G06N3/06

Abstract: A memory array with memory cells arranged in rows and columns. Each memory cell includes source and drain regions with a channel region there between, a floating gate disposed over a first channel region portion, and a second gate disposed over a second channel region portion. A plurality of bit lines each extends along one of the columns and is electrically connected to the drain regions of a first group of one or more of the memory cells in the column and is electrically isolated from the drain regions of a second group of one or more of the memory cells in the column. A plurality of source lines each is electrically connected to the source regions memory cells in one of the columns or rows. A plurality of gate lines each is electrically connected to the second gates of memory cells in one of the columns or rows.

公开(公告)号：US10217850B2

公开(公告)日：2019-02-26

申请号：US15474879

申请日：2017-03-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Chien-Sheng Su ,  Nhan Do ,  Chunming Wang

IPC: H01L29/66 ,  H01L29/788 ,  H01L27/07 ,  H01L29/08 ,  H01L29/423 ,  H01L21/28

Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

公开(公告)号：US10216242B2

公开(公告)日：2019-02-26

申请号：US15610612

申请日：2017-05-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Anh Ly ,  Hung Quoc Nguyen

IPC: G11C5/14 ,  G06F1/26 ,  G06F1/28 ,  G11C7/20 ,  G11C16/30 ,  H03K19/0185 ,  G11C11/4074

Abstract: A system and method for improved power sequencing within an embedded flash memory device is disclosed. Various power-on sequences and power-down sequences for a plurality of voltage sources are utilized to improve the performance of an embedded flash memory device. The plurality of voltage sources can be used for different purposes within the embedded flash memory device.

公开(公告)号：US20180286486A1

公开(公告)日：2018-10-04

申请号：US15905720

申请日：2018-02-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Mark Reiten

IPC: G11C16/24 ,  H01L27/11521 ,  G11C16/04 ,  G11C16/28

CPC classification number: G11C16/24 ,  G06F7/588 ,  G11C16/0425 ,  G11C16/22 ,  G11C16/28 ,  H01L27/11521 ,  H01L29/42328

Abstract: A memory device that generates a unique identifying number, and includes a plurality of memory cells and a controller. Each of the memory cells includes first and second regions formed in a semiconductor substrate, wherein a channel region of the substrate extends between the first and second regions, a floating gate disposed over and insulated from a first portion of the channel region, and a select gate disposed over and insulated from a second portion of the channel region. The controller is configured to apply one or more positive voltages to the first regions of the memory cells while the memory cells are in a subthreshold state for generating leakage current through each of the channel regions, measure the leakage currents, and generate a number based on the measured leakage currents.

公开(公告)号：US20180277174A1

公开(公告)日：2018-09-27

申请号：US15467174

申请日：2017-03-23

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  XIAN LIU ,  NHAN DO

IPC: G11C7/10 ,  G11C8/12 ,  H01L21/28 ,  H01L27/11521 ,  H01L29/423

CPC classification number: G11C7/1006 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/0425 ,  G11C16/08 ,  G11C29/024 ,  G11C2029/1202 ,  G11C2029/1204 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: A system and method are disclosed for performing address fault detection in a flash memory system. An address fault detection array is used to confirm that an activated word line or bit line is the word line or bit line that was actually intended to be activated based upon the received address, which will identify a type of fault where the wrong word line or bit line is activated. The address fault detection array also is used to indicate whether more than one word line or bit line was activated, which will identify a type of fault where two or more word lines or bit lines are activated.

公开(公告)号：US20180268912A1

公开(公告)日：2018-09-20

申请号：US15987735

申请日：2018-05-23

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Xinjie Guo ,  Farnood Merrikh Bayat ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari

IPC: G11C16/34 ,  H01L27/11558 ,  H01L27/11521 ,  G11C16/26 ,  G11C16/10 ,  G11C16/14

CPC classification number: G11C16/3431 ,  G11C7/18 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11558 ,  H01L29/7881

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

公开(公告)号：US20180145253A1

公开(公告)日：2018-05-24

申请号：US15727776

申请日：2017-10-09

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Steven Lemke ,  Santosh Hariharan ,  Hieu Van Tran ,  Nhan Do

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: A method of forming a memory device includes forming a first layer of conductive material having opposing upper and lower surfaces, forming a layer of amorphous silicon on the upper surface of the first layer of conductive material, stripping away the layer of amorphous silicon, wherein some of the amorphous silicon remains in the upper surface of the first layer of conductive material, forming a layer of transition metal oxide material on the upper surface of the first layer of conductive material, and forming a second layer of conductive material on the layer of transition metal oxide material. The method smoothes the upper surface of the bottom electrode, and also provides an bottom electrode upper surface with stable material that is hard to oxidize.

公开(公告)号：US20180144804A1

公开(公告)日：2018-05-24

申请号：US15873872

申请日：2018-01-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/28 ,  G11C16/24 ,  G11C7/06 ,  G11C16/04 ,  G11C16/14

CPC classification number: G11C16/28 ,  G11C7/065 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/24

Abstract: The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors.