公开(公告)号：US09852983B1

公开(公告)日：2017-12-26

申请号：US15428137

申请日：2017-02-08

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Dai Yang Lee

IPC: H01L23/525 ,  H01L21/266 ,  H01L21/768 ,  H01L27/112 ,  G11C17/16

CPC classification number: H01L23/5252 ,  G11C17/16 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/11206

Abstract: A fabricating method of an anti-fuse structure, comprising: providing a substrate having a first conductive plug and a second conductive plug separated from the first conductive plug; forming an amorphous silicon layer on the substrate, wherein a portion of the amorphous silicon layer overlapping the first conductive plug is defined as a first region, and a portion of the amorphous silicon layer overlapping the second conductive plug is defined as a second region; performing an implantation process to the first region and the second region, wherein the first region has a higher doping concentration than the second region; forming a titanium nitride layer on the amorphous silicon layer; and patterning the titanium nitride layer and the amorphous silicon layer.

公开(公告)号：US09735015B1

公开(公告)日：2017-08-15

申请号：US15369878

申请日：2016-12-05

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Kun Ju Li ,  Hsin Jung Liu ,  Wei-Chuan Tsai ,  Min-Chuan Tsai ,  Yi Han Liao ,  Chun-Tsen Lu ,  Chun-Lin Chen ,  Jui-Ming Yang ,  Kuo-Chin Hung

IPC: H01L21/00 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L21/321 ,  H01L21/8234

CPC classification number: H01L21/28123 ,  H01L21/28079 ,  H01L21/3212 ,  H01L21/823456 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor structure, comprising: providing a preliminary structure having a first region and a second region and comprising a plurality of first trenches in the first region; forming a metal layer filling the first trenches covering on the preliminary structure, wherein the metal layer comprises a concave portion in the second region and the concave portion defines an opening; forming a metal nitride layer on the metal layer by an nitride treatment; and performing a planarization process to remove the metal nitride layer and a portion of the metal layer to expose the preliminary structure.

公开(公告)号：US09698047B2

公开(公告)日：2017-07-04

申请号：US14742589

申请日：2015-06-17

Applicant: United Microelectronics Corporation

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Yi-Wei Chen ,  Yung-Feng Cheng ,  Li-Ping Huang ,  Chun-Hsien Huang ,  Chia-Wei Huang ,  Yu-Tse Kuo

IPC: H01L29/78 ,  H01L27/11 ,  H01L21/768 ,  H01L29/66 ,  H01L27/02

CPC classification number: H01L27/0207 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

公开(公告)号：US09570315B2

公开(公告)日：2017-02-14

申请号：US14662142

申请日：2015-03-18

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chueh-Yang Liu ,  Yi-Liang Ye ,  Ted Ming-Lang Guo ,  Yu-Ren Wang

IPC: H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31111 ,  H01L21/0206 ,  H01L21/02238 ,  H01L21/28238 ,  H01L21/823462 ,  H01L29/66545

Abstract: A method of an interfacial oxide layer formation comprises a plurality of steps. The step (S1) is to remove a native oxide layer from a surface of a substrate; the step (S2) is to form an oxide layer on a surface of a substrate by piranha solution (SPM); the step (S3) is to cleaning a surface of the oxide layer by standard clean 1 (SC1), and the step (S4) is to etch he oxide layer by a solution comprising diluted hydrogen fluoride (dHF) and ozonized pure water (DIO3).

Abstract translation: 界面氧化层形成的方法包括多个步骤。 步骤（S1）是从衬底的表面除去天然氧化物层; 步骤（S2）是通过比拉鱼溶液（SPM）在基板的表面上形成氧化物层; 步骤（S3）是通过标准清洁1（SC1）清洁氧化物层的表面，并且步骤（S4）通过包含稀释氟化氢（dHF）和臭氧化纯水（DIO3）的溶液蚀刻氧化物层 ）。

公开(公告)号：US09525037B2

公开(公告)日：2016-12-20

申请号：US14754636

申请日：2015-06-29

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chun-Hong Peng ,  Yu-Hsi Lai

IPC: H01L21/3205 ,  H01L29/423 ,  H01L21/308 ,  H01L21/306 ,  H01L21/311 ,  H01L21/321 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/4236 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/28035 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31105 ,  H01L21/32115 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7813

Abstract: A trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate. The substrate has a trench. The trench is extended downwardly from a surface of the substrate. The gate includes an insertion portion and a symmetrical protrusion portion. The insertion portion is embedded in the trench. The symmetrical protrusion portion is symmetrically protruded over the surface of the substrate.

Abstract translation: 沟槽栅极金属氧化物半导体场效应晶体管包括基板和栅极。 衬底具有沟槽。 沟槽从衬底的表面向下延伸。 门包括插入部分和对称的突出部分。 插入部分嵌入沟槽中。 对称的突出部分在衬底的表面上对称地突出。

公开(公告)号：US09508813B1

公开(公告)日：2016-11-29

申请号：US14706002

申请日：2015-05-07

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Yen-Ming Chen ,  Chiuling Lee ,  Min-Hsuan Tsai ,  Zheng Hong Chen ,  Wei Hsuan Chang ,  Tseng-Hsun Liu

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7835 ,  H01L29/785

Abstract: The present invention provides a transistor comprising a substrate having a surface; a first deep well region in the substrate; a second deep well region in the substrate, isolated from and encircling the first deep well region; a first well region in the substrate and on the first deep well region; two second well regions in the second deep well region and respectively at two opposite sides of the first well region; a source region in the first well region and adjacent to the surface; two drain regions in the two second well regions respectively and adjacent to the surface; two gate structures on the surface, wherein each of the two gate structures is between the source region and one of the drain regions respectively; and a guard ring in the substrate encircling the second deep well region, and on the periphery of the transistor.

Abstract translation: 本发明提供一种晶体管，其包括具有表面的衬底; 衬底中的第一深阱区; 在衬底中的第二深阱区域，从第一深井区域隔离并环绕第一深井区域; 在衬底中和第一深阱区域上的第一阱区; 第二深井区域中的两个第二阱区域和分别在第一阱区域的两个相对侧的两个第二阱区域; 所述第一阱区域中的源极区域并且与所述表面相邻; 分别在两个第二阱区域中与表面相邻的两个漏极区域; 表面上的两个栅极结构，其中两个栅极结构中的每一个分别在源极区域和漏极区域之一之间; 以及在衬底中的围绕第二深阱区域的保护环，并且在晶体管的外围。

公开(公告)号：US20160336337A1

公开(公告)日：2016-11-17

申请号：US14729086

申请日：2015-06-03

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： SUNG-BIN LIN ,  WEN-CHUNG CHANG

IPC: H01L27/115

CPC classification number: H01L27/11563 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/792

Abstract: A method for manufacturing a non-volatile memory with SONOS memory cells, which includes steps of: providing a substrate; forming a first gate oxide layer and a first gate conductive layer onto the substrate; forming a MOS transistor gate by executing a photolithography process on the first gate conductive layer, and then forming an ONO structure on the substrate; and forming a second gate conductive layer on the ONO substrate, and then forming a NVM transistor gate by executing a photolithography process on the second gate conductive layer.

Abstract translation: 一种用于制造具有SONOS存储器单元的非易失性存储器的方法，其包括以下步骤：提供衬底; 在所述衬底上形成第一栅极氧化物层和第一栅极导电层; 通过在第一栅极导电层上执行光刻工艺形成MOS晶体管栅极，然后在衬底上形成ONO结构; 以及在ONO衬底上形成第二栅极导电层，然后通过在第二栅极导电层上执行光刻工艺来形成NVM晶体管栅极。

公开(公告)号：US09490141B2

公开(公告)日：2016-11-08

申请号：US14585210

申请日：2014-12-30

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Wei-Nan Fang ,  Jiann-Shiun Chen ,  Tzu-Yi Chuang

IPC: H01L21/321 ,  H01L21/311 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L21/3212 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28525 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/7684 ,  H01L21/76877

Abstract: A method for planarizing a semiconductor device includes steps herein. A substrate is provided, on which a stop layer is formed. A trench is formed in the substrate. A first semiconductor film is deposited conformally on the stop layer and the trench. A second semiconductor film is deposited to fill the trench and cover the first semiconductor film. A chemical-mechanical polishing process is performed until the stop layer is exposed. A removal rate of the chemical-mechanical polishing process on the first semiconductor film is higher than that on the second semiconductor film. The first dielectric layer on the substrate selectively is removed.

Abstract translation: 半导体器件的平坦化方法包括这里的步骤。 设置有基板，在其上形成有阻挡层。 在衬底中形成沟槽。 第一半导体膜被共形地沉积在停止层和沟槽上。 沉积第二半导体膜以填充沟槽并覆盖第一半导体膜。 执行化学机械抛光工艺，直到停止层暴露。 第一半导体膜上的化学机械抛光工艺的去除率高于第二半导体膜上的去除率。 选择性地去除衬底上的第一介电层。

公开(公告)号：US20160260820A1

公开(公告)日：2016-09-08

申请号：US15156351

申请日：2016-05-17

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： JHEN-CYUAN LI ,  SHUI-YEN LU ,  MAN-LING LU ,  YU-CHENG TUNG ,  CHUNG-FU CHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/306 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823425 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/7848

Abstract: An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in a trench shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.

Abstract translation: 提供一种适于在Si衬底中形成凹槽的蚀刻方法和由其制造的FinFET晶体管。 蚀刻方法包括提供硅衬底，形成在硅衬底上的至少两个栅极结构和设置在硅衬底上的至少两个栅极间隔结构; 在硅衬底上执行第一蚀刻工艺以形成第一凹槽，其具有基部和两个倾斜侧壁，分别上升到栅极结构的各个底部，并分别与基底互连; 以及在所述第一凹槽的所述基底处对所述硅衬底进行第二蚀刻处理，以形成沟槽形状的第二凹槽，其中所述第一凹槽的两个倾斜侧壁分别与所述第二凹槽互连，并且所述第一凹槽 蚀刻工艺与第二蚀刻工艺基本不同。

公开(公告)号：US09378958B2

公开(公告)日：2016-06-28

申请号：US13729034

申请日：2012-12-28

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chang-Tzu Wang ,  Yu-Chun Chen ,  Tien-Hao Tang

IPC: H01L23/60 ,  H01L21/265 ,  H01L27/02

CPC classification number: H01L21/266 ,  H01L21/265 ,  H01L23/60 ,  H01L27/0277 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided. Plural isolation structures, a well region, a first conductive region and a second conductive region are formed in the semiconductor substrate. The well region contains first type conducting carriers. The first conductive region and the second conductive region contain second type conducting carriers. Then, a mask layer is formed on the surface of the semiconductor substrate, wherein a part of the first conductive region is exposed. Then, a first implantation process is performed to implant the second type conducting carriers into the well region by using the mask layer as an implantation mask, so that a portion of the first type conducting carriers of the well region is electrically neutralized and a first doped region is formed under the exposed part of the first conductive region.

Abstract translation: 一种制造静电放电保护结构的方法包括以下步骤。 首先，提供半导体衬底。 在半导体衬底中形成多个隔离结构，阱区，第一导电区和第二导电区。 阱区包含第一类导电载体。 第一导电区域和第二导电区域包含第二导电载体。 然后，在半导体衬底的表面上形成掩模层，其中露出第一导电区域的一部分。 然后，通过使用掩模层作为注入掩模，执行第一注入工艺以将第二类型导电载体注入阱区，使得阱区的第一类导电载体的一部分被电中和，并且第一掺杂 区域形成在第一导电区域的暴露部分下方。