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    OPTIMIZATION TECHNIQUE OF GENERALIZED DISJUNCTIVE SEMI/ANTI JOIN
    61.
    发明申请
    OPTIMIZATION TECHNIQUE OF GENERALIZED DISJUNCTIVE SEMI/ANTI JOIN 审中-公开
    通用分光光度计的优化技术

    公开(公告)号：US20140067789A1

    公开(公告)日：2014-03-06

    申请号：US13603302

    申请日：2012-09-04

    申请人： Rafi Ahmed ,  Chun-Chieh Lin ,  Mohamed Zait

    发明人： Rafi Ahmed ,  Chun-Chieh Lin ,  Mohamed Zait

    IPC分类号： G06F17/30

    摘要： A method, apparatus, and stored instructions are provided for transforming a query representation by unnesting a predicate condition that is based on whether or not a result exists for a subquery of the predicate condition. An initial query representation is received. The initial query representation represents an initial query that includes an EXISTS-equivalent predicate or a NOT-EXISTS-equivalent predicate and at least one other predicate in a disjunction. The initial query representation is transformed into a semantically equivalent transformed query representation that represents a transformed query. The transformed query includes, instead of the EXISTS-equivalent predicate or a NOT-EXISTS-equivalent predicate, a join operator that references the data object. The transformed query representation, when used for execution, causes the at least one other predicate to be applied separately from a join operation caused by the join operator such that execution of the initial representation is semantically equivalent to execution of the transformed representation.

    摘要翻译： 提供了一种方法，装置和存储的指令，用于通过不知道基于谓词条件的子查询的结果是否存在的谓词条件来转换查询表示。 收到初始查询表示。 初始查询表示代表一个初始查询，其中包含EXISTS等效谓词或NOT-EXISTS等价谓词和至少一个其他谓词。 初始查询表示被转换成表示变换查询的语义上等同的变换查询表示。 转换后的查询包括引用数据对象的连接运算符，而不是EXISTS等效谓词或NOT-EXISTS等效谓词。 经变换的查询表示当用于执行时，使至少一个其他谓词与由连接运算符引起的连接操作分开应用，使得初始表示的执行在语义上等同于转换表示的执行。

    NONVOLATILE MEMORY AND FABRICATION METHOD THEREOF
    63.
    发明申请
    NONVOLATILE MEMORY AND FABRICATION METHOD THEREOF 有权
    非易失性存储器及其制造方法

    公开(公告)号：US20110059592A1

    公开(公告)日：2011-03-10

    申请号：US12943487

    申请日：2010-11-10

    申请人： Tseung-Yuen TSENG ,  Chun-Chieh Lin ,  Chao-Cheng Lin

    发明人： Tseung-Yuen TSENG ,  Chun-Chieh Lin ,  Chao-Cheng Lin

    IPC分类号： H01L21/02

    CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/1625

    摘要： Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO3 film is disposed over the metal layer. A resistor layer comprising a SrZrO3 film is disposed on the buffer layer. A top electrode is disposed on the resistor layer.

    摘要翻译： 公开了在基板上形成的非易失性存储器和制造方法。 包含金属层的底部电极设置在基板上。 包含LaNiO3膜的缓冲层设置在金属层上。 包含SrZrO 3膜的电阻层设置在缓冲层上。 顶电极设置在电阻层上。

    DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area
    68.
    发明授权
    DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area 有权
    DRAM电容器结构具有增加的电极支持，用于防止工艺损坏和暴露的电极表面，以增加电容器面积

    公开(公告)号：US07161204B2

    公开(公告)日：2007-01-09

    申请号：US11098112

    申请日：2005-04-04

    申请人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Fu-Liang Yang ,  Chia-Hui Lin ,  Chanming Hu

    发明人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Fu-Liang Yang ,  Chia-Hui Lin ,  Chanming Hu

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L27/10817 ,  H01L28/91

    摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

    摘要翻译： 实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。 该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。 在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。 然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案化，以在电容器之间提供保护层间电介质结构。 保护结构可防止在后续处理期间损坏底部电极。 蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。 在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

    A Recessed Polysilicon Gate Structure for a Strained Silicon MOSFET Device
    69.
    发明申请
    A Recessed Polysilicon Gate Structure for a Strained Silicon MOSFET Device 有权
    用于应变硅MOSFET器件的嵌入式多晶硅栅极结构

    公开(公告)号：US20060009001A1

    公开(公告)日：2006-01-12

    申请号：US10864952

    申请日：2004-06-10

    申请人： Yi-Chun Huang ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Lawrence Sheu ,  Huan-Jan Tao ,  Chih-Hsin Ko ,  Chun-Chieh Lin

    发明人： Yi-Chun Huang ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Lawrence Sheu ,  Huan-Jan Tao ,  Chih-Hsin Ko ,  Chun-Chieh Lin

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/76

    CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

    摘要： Abstract of the Disclosure A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portion reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

    摘要翻译： 发明内容已经开发出通过使用相邻和周围的硅 - 锗形状在应变硅层中形成用于MOSFET器件的沟道区的方法。 该方法同时形成导电栅极结构的顶部中的凹部并且在半导体衬底的不被栅极结构占据的部分中，或者位于导电栅极结构的侧面上的虚设间隔物。 选择性限定的凹槽将用于随后容纳硅锗形状，其中硅 - 锗形状位于半导体衬底的凹陷中，从而诱导期望的应变通道区域。 导电栅极结构和半导体衬底部分的凹陷减少了在合金层的外延生长期间跨越侧壁间隔物表面的硅 - 锗桥接的风险，从而降低了栅极到衬底泄漏或短路的风险。

    Semiconductor device substrate with embedded capacitor
    70.
    发明申请
    Semiconductor device substrate with embedded capacitor 有权
    具有嵌入式电容器的半导体器件衬底

    公开(公告)号：US20060003522A1

    公开(公告)日：2006-01-05

    申请号：US10881372

    申请日：2004-06-30

    申请人： Chun-Chieh Lin ,  Wen-Chin Lee

    发明人： Chun-Chieh Lin ,  Wen-Chin Lee

    IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L21/8242

    CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10835 ,  H01L27/10858 ,  H01L27/10861 ,  H01L27/1203 ,  H01L28/55 ,  H01L28/82

    摘要： A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.

    摘要翻译： 一种用于形成半导体器件的方法，该半导体器件包括具有嵌入式电容器结构的绝缘体上硅（SOI）衬底的DRAM单元结构，包括提供包括上覆的第一电绝缘层的衬底; 在所述第一电绝缘层上形成第一导电层以形成第一电极; 在所述第一电极上形成电容器电介质层; 在所述电容器介电层上形成第二导电层以形成第二电极; 在所述第二电极上形成第二电绝缘层; 以及在所述第二电极上形成单晶硅层以形成包括第一电容器结构的SOI衬底。