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    Matching paths in a multiple path analog-to-digital converter
    63.
    发明授权
    Matching paths in a multiple path analog-to-digital converter 有权

    公开(公告)号：US09780800B1

    公开(公告)日：2017-10-03

    申请号：US15269043

    申请日：2016-09-19

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Aniruddha Satoskar ,  Daniel J. Allen ,  Edmund Mark Schneider ,  Saurabh Singh ,  John L. Melanson

    IPC: H03M1/06

    CPC classification number: H03M1/0626 ,  H03M1/0607 ,  H03M1/0612 ,  H03M1/188

    Abstract: A method may include processing an analog input signal with a first processing path configured to generate a first digital signal based on the analog input signal; processing the analog input signal with a second processing path configured to generate a second digital signal based on the analog input signal, and adapting a response of an adaptive filter configured to generate a filtered digital signal from the second digital signal to reduce a difference between the filtered digital signal and the first digital signal. The method may additionally or alternatively include determining nonlinearities present in the second processing path based on comparison of the first digital signal and the second digital signal, and applying a linear correction to the second digital signal to generate a corrected second digital signal with decreased nonlinearity from that of the second digital signal.

    Ring frequency divider
    67.
    发明授权
    Ring frequency divider 有权
    振铃分频器

    公开(公告)号：US09595971B2

    公开(公告)日：2017-03-14

    申请号：US15159750

    申请日：2016-05-19

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Yousof Mortazavi ,  John L. Melanson ,  Aaron Brennan

    IPC: H03K23/54 ,  G04F10/02 ,  H03M1/50 ,  H03K3/03 ,  H03L7/089 ,  H03L7/099 ,  H03K3/037

    CPC classification number: H03K23/54 ,  G04F10/02 ,  H03K3/0315 ,  H03K3/0372 ,  H03L7/0891 ,  H03L7/0995 ,  H03M1/50

    Abstract: A circuit for a divider or counter may include a frequency divider having multiple rings for dividing an input frequency to obtain an output frequency. The first and second rings may include an odd-numbered plurality of elements, such as inverters, wherein each inverter of a ring is coupled to another inverter of the ring in a circular chain. An input frequency may be input to a power supply input of inverters of the first ring. The second ring inverters may be coupled at a power supply input to output nodes of the first ring inverters, which results in the second ring operating at a divisional rate of the first frequency given by (N−1), where N is the number of inverters in the ring. The circuits may be used in frequency dividers and counters, such as in phase-locked loops (PLLs) and analog-to-digital converters (ADCs).

    Abstract translation: 用于分频器或计数器的电路可以包括具有用于分频输入频率以获得输出频率的多个环的分频器。 第一和第二环可以包括奇数多个元件，例如逆变器，其中环的每个反相器以环形链耦合到环的另一反相器。 输入频率可以被输入到第一环的反相器的电源输入端。 第二环形反相器可以在电源输入处耦合到第一环形逆变器的输出节点，这导致第二环以由（N-1）给出的第一频率的分割速率操作，其中N是 逆变器在环。 这些电路可用于分频器和计数器，例如锁相环（PLL）和模数转换器（ADC）。

    SWITCHED-CAPACITOR BATTERY MANAGEMENT POWER SUPPLY PROVIDING POWER FROM PORTIONS OF A MULTI-CELL BATTERY
    68.
    发明申请
    SWITCHED-CAPACITOR BATTERY MANAGEMENT POWER SUPPLY PROVIDING POWER FROM PORTIONS OF A MULTI-CELL BATTERY 有权

    公开(公告)号：US20250015715A1

    公开(公告)日：2025-01-09

    申请号：US18347458

    申请日：2023-07-05

    Applicant: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.

    Inventor： John L. Melanson

    IPC: H02M3/07 ,  G01R31/396 ,  H02J7/00 ,  H02J7/34

    Abstract: A circuit for powering a battery monitor in devices powered by a multi-cell battery, provides efficient use of energy in standby operating modes of battery-powered devices. The circuit includes a switched-capacitor network having at least two capacitors and at least two corresponding first switches. The capacitors have first terminals intermittently coupled in alternation to first terminals of corresponding cells or groups of cells of the multi-cell battery and second terminals of the corresponding cells or groups of cells of the multi-cell battery by the first switches according to a first clock signal. The switched-capacitor network also includes at least one second switch that intermittently couples second terminals of the at least two capacitors to an output node according to the first clock signal. The output node is configured to supply power to the battery monitor. The circuit also includes a clocking circuit for generating the first clock signal.

    Dynamic state management of a phase-lock loop (PLL)
    69.
    发明授权
    Dynamic state management of a phase-lock loop (PLL) 有权

    公开(公告)号：US12088308B1

    公开(公告)日：2024-09-10

    申请号：US17972739

    申请日：2022-10-25

    Applicant: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.

    Inventor： Stewart G. Kenly ,  Amar Vellanki ,  John L. Melanson

    IPC: H03L7/087 ,  H03L7/097 ,  H03L7/099

    CPC classification number: H03L7/087 ,  H03L7/097 ,  H03L7/0992

    Abstract: A phase-lock loop (PLL) circuit provides continuous closed-loop operation when switching between operating modes, which may be selection between multiple oscillators, multiple power modes or frequency divider/multipliers of an local clock generator having one or more oscillator circuits, or other changes that may disrupt operation of the PLL. The PLL includes a loop filter having an input coupled to an output of a phase-frequency comparator that compares the output of the oscillator circuit to a reference and a control circuit for storing and restoring the complete state of the loop filter from the storage in response to a change of operating mode, so that a lock time of the phase-lock loop circuit is reduced when selection of one of the at least two selectable different output frequency ranges of the local clock generator is changed.

    System and method for semiconductor device random telegraph sequence noise testing
    70.
    发明授权
    System and method for semiconductor device random telegraph sequence noise testing 有权

    公开(公告)号：US11674995B2

    公开(公告)日：2023-06-13

    申请号：US17148371

    申请日：2021-01-13

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Aleksey S. Khenkin ,  John C. Tucker ,  John L. Melanson ,  Jeffrey A. Weintraub

    IPC: G01R31/26 ,  G01R31/28

    CPC classification number: G01R31/2646 ,  G01R31/2875 ,  G01R31/2877

    Abstract: A method for screening a semiconductor device for production of excessive random telegraph sequence (RTS) noise includes measuring noise of the semiconductor device at a first temperature, changing the temperature of the semiconductor device to a second temperature different from the first temperature, measuring noise of the semiconductor device at the second temperature, extracting a characteristic of the measured noise at the first and second temperatures (e.g., standard deviation, HMM output, frequency domain spectrum of time domain noise measurement), making a comparison of the extracted first and second noise characteristics, and making a determination whether the semiconductor device produces excessive RTS noise based on whether the comparison is above a predetermined threshold. Two different bias conditions of the device may be employed rather than, or in addition to, the two different temperatures.

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