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140 条记录 (耗时 0.051 秒)

    Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
    61.
    发明授权
    Local bit lines and methods of selecting the same to access memory elements in cross-point arrays 有权
    本地位线及其选择方法可以访问交叉点阵列中的存储器元件

    公开(公告)号：US08897050B2

    公开(公告)日：2014-11-25

    申请号：US13588461

    申请日：2012-08-17

    申请人： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Namala

    发明人： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Namala

    IPC分类号： G11C5/02 ,  H01L21/82 ,  G11C8/00 ,  G11C11/00

    CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C8/00 ,  G11C11/00 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/77 ,  H01L21/82 ,  H01L27/2481 ,  H01L45/16

    摘要： Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

    摘要翻译： 实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。 在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。 交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。 每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。 还包括设置在X线的子集和Y线部分的组之间的存储器元件。 在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。

    Movable terminal in a two terminal memory array
    63.
    发明授权
    Movable terminal in a two terminal memory array 失效
    两个终端存储器阵列中的可移动终端

    公开(公告)号：US07701834B2

    公开(公告)日：2010-04-20

    申请号：US11037971

    申请日：2005-01-18

    申请人： Darrell Rinerson ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Lawerence Schloss

    发明人： Darrell Rinerson ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Lawerence Schloss

    IPC分类号： G11B9/00

    CPC分类号： G11B9/08 ,  B82Y10/00 ,  G11B9/1445

    摘要： A movable terminal in a two terminal memory array. A storage medium is disposed between two terminals, one of the terminals being movable relative to the second terminal. Either one of the terminals or both terminals might actually move, resulting in one terminal being moved relative to the other terminal. A memory element disposed between the two terminals has a conductance that is responsive to a write voltage across the electrodes.

    摘要翻译： 二端存储器阵列中的可动端子。 存储介质设置在两个端子之间，其中一个端子可相对于第二端子移动。 终端或两个终端中的任一个可能实际上移动，导致一个终端相对于另一个终端移动。 设置在两个端子之间的存储元件具有响应电极两端的写入电压的电导。

    Two-cycle sensing in a two-terminal memory array having leakage current
    64.
    发明授权
    Two-cycle sensing in a two-terminal memory array having leakage current 有权
    具有漏电流的双端存储器阵列中的双周期感测

    公开(公告)号：US07372753B1

    公开(公告)日：2008-05-13

    申请号：US11583676

    申请日：2006-10-19

    申请人： Darrell Rinerson ,  Christophe Chevallier ,  Chang Hua Siau

    发明人： Darrell Rinerson ,  Christophe Chevallier ,  Chang Hua Siau

    IPC分类号： G11C7/02

    CPC分类号： G11C11/16 ,  G11C13/004 ,  G11C2013/0057

    摘要： A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.

    摘要翻译： 双端存储器阵列包括多个第一和第二导电迹线。 地址单元可操作地对所选择的第一和第二导电迹线对施加选择电压，并将非选择电压电势施加到未选择的迹线。 在所选择的第一导电迹线中流动的总电流和流过未选择的第二导电迹线的漏电流在一个周期或两个周期的预读操作中由感测单元感测。 总和漏电流可以与参考信号组合以导出指示表示存储的数据的多个电导率分布之一的数据信号。 电导率分布可以存储在与所选择的第一和第二导电迹线电串联的电阻状态存储元件中。

    TWO-CYCLE SENSING IN A TWO-TERMINAL MEMORY ARRAY HAVING LEAKAGE CURRENT
    65.
    发明申请
    TWO-CYCLE SENSING IN A TWO-TERMINAL MEMORY ARRAY HAVING LEAKAGE CURRENT 有权
    具有漏电流的两端存储器阵列中的双周期感测

    公开(公告)号：US20080094929A1

    公开(公告)日：2008-04-24

    申请号：US11583676

    申请日：2006-10-19

    申请人： Darrell Rinerson ,  Christophe Chevallier ,  Chang Hua Siau

    发明人： Darrell Rinerson ,  Christophe Chevallier ,  Chang Hua Siau

    IPC分类号： G11C11/00 ,  G11C7/02

    CPC分类号： G11C11/16 ,  G11C13/004 ,  G11C2013/0057

    摘要： A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.

    摘要翻译： 双端存储器阵列包括多个第一和第二导电迹线。 地址单元可操作地对所选择的第一和第二导电迹线对施加选择电压，并将非选择电压电势施加到未选择的迹线。 在所选择的第一导电迹线中流动的总电流和流过未选择的第二导电迹线的漏电流在一个周期或两个周期的预读操作中由感测单元感测。 总和漏电流可以与参考信号组合以导出指示表示存储的数据的多个电导率分布之一的数据信号。 电导率分布可以存储在与所选择的第一和第二导电迹线电串联的电阻状态存储元件中。

    Memory device using ion implant isolated conductive metal oxide
    70.
    发明授权
    Memory device using ion implant isolated conductive metal oxide 有权
    使用离子注入隔离导电金属氧化物的存储器件

    公开(公告)号：US08268667B2

    公开(公告)日：2012-09-18

    申请号：US13215895

    申请日：2011-08-23

    申请人： Darrell Rinerson ,  Robin Cheung ,  David Hansen ,  Steven Longcor ,  Rene Meyer ,  Jonathan Bornstein ,  Lawrence Schloss

    发明人： Darrell Rinerson ,  Robin Cheung ,  David Hansen ,  Steven Longcor ,  Rene Meyer ,  Jonathan Bornstein ,  Lawrence Schloss

    IPC分类号： H01L21/00

    CPC分类号： F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

    摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

    摘要翻译： 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOx，LaSrCoOx，LaNiOx等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。