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115 条记录 (耗时 0.029 秒)

    System and method for mitigating oxide growth in a gate dielectric
    62.
    发明授权
    System and method for mitigating oxide growth in a gate dielectric 有权
    用于减轻栅极电介质中的氧化物生长的系统和方法

    公开(公告)号：US06921703B2

    公开(公告)日：2005-07-26

    申请号：US10436848

    申请日：2003-05-13

    申请人： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

    发明人： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

    IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/28202 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

    摘要： Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

    摘要翻译： 可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。 氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。 维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

    Nickel silicide formation for semiconductor components
    64.
    发明授权
    Nickel silicide formation for semiconductor components 有权
    半导体元件的硅化镍形成

    公开(公告)号：US08546259B2

    公开(公告)日：2013-10-01

    申请号：US11861421

    申请日：2007-09-26

    申请人： Juanita DeLoach ,  Jiong-Ping Lu ,  Haowen Bu

    发明人： Juanita DeLoach ,  Jiong-Ping Lu ,  Haowen Bu

    IPC分类号： H01L21/44

    CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/7833

    摘要： Semiconductor components are often fabricated that include a nickel silicide layer, e.g., as part of a gate electrode in a transistor component, which may be formed by forming a layer of nickel on a silicon-containing area of the semiconductor substrate, followed by thermally annealing the semiconductor substrate to produce a nickel silicide. However, nickel may tend to diffuse into silicon during the thermal anneal, and may form crystals that undesirably increase the sheet resistance in the transistor. Carbon may be placed with the nickel to serve as a diffusion suppressant and/or to prevent nickel crystal formation during thermal annealing. Methods are disclosed for utilizing this technique, as well as semiconductor components formed in accordance with this technique.

    摘要翻译： 通常制造半导体部件，其包括硅化镍层，例如，作为晶体管部件中的栅电极的一部分，其可以通过在半导体衬底的含硅区域上形成镍层，然后进行热退火 半导体衬底以产生硅化镍。 然而，镍可能在热退火期间扩散到硅中，并且可能形成不期望地增加晶体管中的薄层电阻的晶体。 碳可以与镍一起放置以用作扩散抑制剂和/或防止在热退火期间形成镍晶体。 公开了利用该技术的方法以及根据该技术形成的半导体部件。

    Hydrogen-Blocking Film for Ferroelectric Capacitors
    65.
    发明申请
    Hydrogen-Blocking Film for Ferroelectric Capacitors 审中-公开
    用于铁电电容器的氢封闭膜

    公开(公告)号：US20130056811A1

    公开(公告)日：2013-03-07

    申请号：US13432736

    申请日：2012-03-28

    申请人： Bo-Yang Lin ,  Yen Lee ,  Haowen Bu ,  Mark Robert Visokay

    发明人： Bo-Yang Lin ,  Yen Lee ,  Haowen Bu ,  Mark Robert Visokay

    IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L29/92

    CPC分类号： H01L21/02225 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/57

    摘要： An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH4) and nitrogen (N2) are provided to a parallel-plate plasma reactor, in which energy is capacitively coupled to the plasma, and in which the wafer being processed has been placed at a support electrode. Low-frequency RF energy (e.g., 360 kHz) is applied to the support electrode; high-frequency RF energy (e.g., 13.56 MHz) is optionally provided to the parallel electrode. Process temperature is above 350° C., at a pressure of about 2.5 torr. Any hydrogen present in the resulting silicon nitride film is bound by N—H bonds rather than Si—H bonds, and is thus more strongly bound to the film. The silicon nitride can serve as passivation for ferroelectric material that may degrade electrically if contaminated by hydrogen.

    摘要翻译： 通过等离子体增强化学气相沉积（PECVD）沉积氮化硅的无氨方法。 将硅烷（SiH4）和氮（N2）的源气体提供给平行板等离子体反应器，其中能量电容耦合到等离子体，并且其中待处理的晶片已经被放置在支撑电极处。 将低频RF能量（例如，360kHz）施加到支撑电极; 可选地，将高频RF能量（例如，13.56MHz）提供给并联电极。 工艺温度高于350℃，压力约为2.5托。 存在于所得氮化硅膜中的任何氢由N-H键而不是Si-H键结合，因此与膜更牢固地结合。 氮化硅可用作铁电材料的钝化剂，如果被氢气污染，则可能会电解。

    Systems and methods that selectively modify liner induced stress
    66.
    发明授权
    Systems and methods that selectively modify liner induced stress 有权
    系统和方法选择性地修改衬垫引起的应力

    公开(公告)号：US07939400B2

    公开(公告)日：2011-05-10

    申请号：US12235766

    申请日：2008-09-23

    申请人： Ting Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

    发明人： Ting Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

    摘要翻译： 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

    Using oxynitride spacer to reduce parasitic capacitance in CMOS devices
    67.
    发明授权
    Using oxynitride spacer to reduce parasitic capacitance in CMOS devices 有权
    使用氮氧化物间隔物来减少CMOS器件中的寄生电容

    公开(公告)号：US07667275B2

    公开(公告)日：2010-02-23

    申请号：US10938179

    申请日：2004-09-11

    申请人： Yuanning Chen ,  Haowen Bu ,  Kaiping Liu

    发明人： Yuanning Chen ,  Haowen Bu ,  Kaiping Liu

    IPC分类号： H01L23/62

    CPC分类号： H01L29/6656 ,  H01L21/823864 ,  H01L29/66598 ,  H01L29/7833

    摘要： A complementary metal oxide semiconductor (CMOS) device has a substrate 100, a gate structure 108 disposed atop the substrate, and spacers 250, deposited on opposite sides of the gate structure 108 to govern formation of deep source drain regions S, D in the substrate. Spacers 250 are formed of an oxynitride (SiOxNyCz) wherein x and y are non-zero but z may be zero or greater; such oxynitride spacers reduce parasitic capacitance, thus improving device performance. A method of fabricating a portion of a complementary metal oxide semiconductor (CMOS) device involves providing a substrate 100, forming a gate structure 108 over the substrate, depositing a first layer 104 atop the substrate on opposite sides of the gate structure to govern formation of deep source drain regions in the substrate, depositing an oxynitride (SiOxNyCz) layer 250 atop the first layer (in which x and y are non-zero but z may be zero or greater), depositing a second layer 112 atop the oxynitride layer, and depositing a nitride layer 114B atop the second layer.

    摘要翻译： 互补金属氧化物半导体（CMOS）器件具有衬底100，设置在衬底顶部的栅极结构108和沉积在栅极结构108的相对侧上的间隔物250，以控制衬底中的深源极漏极区S，D的形成 。 间隔物250由氧氮化物（SiOxNyCz）形成，其中x和y不为零，但z可以为零或更大; 这种氧氮化物间隔物减少寄生电容，从而提高器件性能。 制造互补金属氧化物半导体（CMOS）器件的一部分的方法包括提供衬底100，在衬底上形成栅极结构108，在栅极结构的相对侧上沉积衬底顶部的第一层104，以形成 在衬底中的深源极漏极区域，在第一层上方沉积氧氮化物（SiO x N y C z）层250（其中x和y不为零但z可以为零或更大），在氮氧化物层的顶部沉积第二层112，以及 在第二层上方沉积氮化物层114B。

    Semiconductor doping with improved activation
    68.
    发明授权
    Semiconductor doping with improved activation 有权
    半导体掺杂改善激活

    公开(公告)号：US07572716B2

    公开(公告)日：2009-08-11

    申请号：US11739981

    申请日：2007-04-25

    申请人： Haowen Bu ,  Shashank S. Ekbote ,  Borna Obradovic ,  Srinivasan Chakravarthi

    发明人： Haowen Bu ,  Shashank S. Ekbote ,  Borna Obradovic ,  Srinivasan Chakravarthi

    IPC分类号： H01L21/425

    CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/324

    摘要： A method is disclosed for doping a target area of a semiconductor substrate, such as a source or drain region of a transistor, with an electronically active dopant (such as an N-type dopant used to create active areas in NMOS devices, or a P-type dopant used to create active areas in PMOS devices) having a well-controlled placement profile and strong activation. The method comprises placing a carbon-containing diffusion suppressant in the target area at approximately 50% of the concentration of the dopant, and activating the dopant by an approximately 1,040 degree Celsius thermal anneal. In many cases, a thermal anneal at such a high temperature induces excessive diffusion of the dopant out of the target area, but this relative concentration of carbon produces a heretofore unexpected reduction in dopant diffusion during such a high-temperature thermal anneal. The disclosure also pertains to semiconductor components produced in this manner, and various embodiments and improvements of such methods for producing such components.

    摘要翻译： 公开了一种用于将诸如晶体管的源极或漏极区域的半导体衬底的目标区域掺杂到电子有源掺杂剂（例如用于在NMOS器件中产生有源区域的N型掺杂剂）或P 用于在PMOS器件中产生有源区）的具有良好控制的放置曲线和强激活。 该方法包括将目标区域中的含碳扩散抑制剂置于掺杂剂浓度的约50％处，并使掺杂剂活化约1,040摄氏度的热退火。 在许多情况下，在这样高的温度下的热退火引起掺杂剂离开目标区域的过度扩散，但这种相对浓度的碳在这样的高温热退火期间产生了掺杂剂扩散的意外的减少。 本公开还涉及以这种方式制造的半导体部件，以及用于制造这种部件的这种方法的各种实施例和改进。

    Systems and methods that selectively modify liner induced stress
    69.
    发明授权
    Systems and methods that selectively modify liner induced stress 有权
    系统和方法选择性地修改衬垫引起的应力

    公开(公告)号：US07442597B2

    公开(公告)日：2008-10-28

    申请号：US11049275

    申请日：2005-02-02

    申请人： Ting Y. Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

    发明人： Ting Y. Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

    摘要翻译： 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。