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    Dll Circuit
    61.
    发明申请
    Dll Circuit 审中-公开
    Dll电路

    公开(公告)号：US20070279111A1

    公开(公告)日：2007-12-06

    申请号：US10589403

    申请日：2005-02-09

    申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

    发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  G11C7/1072 ,  G11C7/222 ,  G11C16/32 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/133 ,  H03K2005/00019 ,  H03L7/0818

    摘要： A DLL circuit having a phase comparison circuit for comparing phases of a reference clock and a delay clock and a variable delay addition circuit for adjusting delay amount according to a signal from the phase comparison circuit comprises a means for inputting a first signal latched at a logic “1” by start of 1 clock cycle of an internal clock to the variable delay addition circuit through a dummy delay at the start of burst and a means for detecting duration time of the logic “1” of the first signal input by the variable delay addition circuit through the dummy delay until the end of the 1 clock cycle of the internal clock and setting an initial value of delay amount of the variable delay addition circuit based on the duration time.

    摘要翻译： 具有用于比较参考时钟和延迟时钟的相位的相位比较电路的DLL电路和用于根据来自相位比较电路的信号调整延迟量的可变延迟加法电路包括用于输入锁存在逻辑上的第一信号的装置 通过在突发开始时的虚拟延迟，将内部时钟的1个时钟周期开始到可变延迟加法电路的“1”和用于检测由可变延迟输入的第一信号的逻辑“1”的持续时间的装置 通过虚拟延迟的加法电路，直到内部时钟的1个时钟周期结束，并且基于持续时间设置可变延迟加法电路的延迟量的初始值。

    Non-volatile semiconductor memory and method of manufacturing the same
    62.
    发明授权
    Non-volatile semiconductor memory and method of manufacturing the same 失效
    非易失性半导体存储器及其制造方法

    公开(公告)号：US5824583A

    公开(公告)日：1998-10-20

    申请号：US949819

    申请日：1997-10-14

    申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

    发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

    CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

    摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.

    摘要翻译： 本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。 每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。 浮动栅极部分地覆盖沟道区域。 因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。 浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。 多个存储单元串联连接以构成基本块。 相邻的基本块由增强型MOS晶体管分开。 在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。 此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

    Non-volatile semiconductor memory and method of manufacturing the same
    63.
    发明授权
    Non-volatile semiconductor memory and method of manufacturing the same 失效
    非易失性半导体存储器及其制造方法

    公开(公告)号：US5323039A

    公开(公告)日：1994-06-21

    申请号：US499342

    申请日：1990-06-21

    申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

    发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/68

    CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

    摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.

    摘要翻译： PCT No.PCT / JP89 / 00942 Sec。 371 1990年6月21日第 102（e）日期1990年6月21日PCT提交1989年9月14日PCT公布。 公开号WO90 / 04855 日期为1990年5月3日。本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。 每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。 浮动栅极部分地覆盖沟道区域。 因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。 浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。 多个存储单元串联连接以构成基本块。 相邻的基本块由增强型MOS晶体管分开。 在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。 此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

    Erase circuitry for a non-volatile semiconductor memory device
    65.
    发明授权
    Erase circuitry for a non-volatile semiconductor memory device 失效
    擦除非易失性半导体存储器件的电路

    公开(公告)号：US5095461A

    公开(公告)日：1992-03-10

    申请号：US457859

    申请日：1989-12-27

    申请人： Tadashi Miyakawa ,  Masamichi Asano

    发明人： Tadashi Miyakawa ,  Masamichi Asano

    IPC分类号： G11C16/14

    CPC分类号： G11C16/14

    摘要： An memory cell array includes a plurality of electrically erasable and programmable memory cell transistors which are arranged in a matrix form and each of which includes a source region, drain region, floating gate, erasing gate and control gate. The patterns of the control gates and the source regions in the memory cell array are arranged in parallel along the row direction of the memory cell array and the patterns of the erasing gates are arranged to extend in the column direction of the memory cell array. The memory cell transistors in the memory cell array are selected by a row decoder and a column decoder. An erasing circuit functions to erase memory data of each memory cell transistor by applying an erasing potential to the erasing gate of the memory cell transistor. A source potential generation circuit applies a first potential for programming and readout to the source region of a memory cell transistor selected by the row and column decoders when data is programmed into or read out from the selected memory cell transistor and applies a second potential which is higher than the first potential and lower than the erasing potential to the source region of each memory cell transistor when memory data of each memory cell transistor is erased by the erasing circuit. A potential difference between the source region and the erasing gate of the memory cell transistor in the erasing mode is reduced by the second potential output from the source potential generation circuit.

    摘要翻译： 存储单元阵列包括以矩阵形式布置的多个电可擦除可编程存储单元晶体管，每个晶体管包括源区，漏区，浮置栅，擦除栅和控制栅。 存储单元阵列中的控制栅极和源极区域的图案沿着存储单元阵列的行方向并排布置，并且擦除栅极的图案被布置成在存储单元阵列的列方向上延伸。 存储单元阵列中的存储单元晶体管由行解码器和列解码器选择。 擦除电路用于通过向存储单元晶体管的擦除栅极施加擦除电位来擦除每个存储单元晶体管的存储器数据。 当数据被编程到所选择的存储单元晶体管中或从所选择的存储单元晶体管中读出时，源极电位产生电路将用于编程和读出的第一电位施加到由行和列解码器选择的存储单元晶体管的源极区域，并施加第二电位， 当每个存储单元晶体管的存储器数据被擦除电路擦除时，高于第一电位并且低于每个存储单元晶体管的源极区的擦除电位。 在擦除模式下存储单元晶体管的源极区域和擦除栅极之间的电位差由源极电位产生电路的第二个电位输出减小。

    Nonvolatile semiconductor memory
    66.
    发明授权
    Nonvolatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US5053841A

    公开(公告)日：1991-10-01

    申请号：US423362

    申请日：1989-10-18

    申请人： Tadashi Miyakawa ,  Masamichi Asano ,  Tadayuki Taura ,  Atsushi Shoji ,  Michiharu Inami

    发明人： Tadashi Miyakawa ,  Masamichi Asano ,  Tadayuki Taura ,  Atsushi Shoji ,  Michiharu Inami

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L29/7886

    摘要： A nonvolatile semiconductor memory includes a cell array in which electrically erasable programmable nonvolatile semiconductor memory cells, each using a cell transistor having source and drain regions in a semiconductor substrate, and a gate electrode with a three-layered structure on the semiconductor substrate are arranged in a matrix form. In the gate electrode having the three-layered structure, a first-layer floating gate electrode opposes a semiconductor substrate surface through a first gate insulating film, and a second- or third-layer gate electrode serves as one of erase and control gate electrodes. The erase gate electrode opposes a part of the floating gate electrode through a tunnel insulating film, and the control gate electrode opposes the floating gate electrode through a second gate insulating film. The erase and control gate electrodes are arranged to be parallel to each other, and to be perpendicular to the source and drain regions. Of two cell transistors adjacent to each other in a length direction of the channel region, the source region of one cell transistor is common to the drain region of the other cell transistor, and the cell transistors adjacent to each other in the widthwise direction of the channel region are element-isolated by an element isolation region formed in the semiconductor substrate between the channel regions.

    摘要翻译： 非易失性半导体存储器包括：单元阵列，其中在半导体衬底中使用具有源极和漏极区域的单元晶体管和半导体衬底上具有三层结构的栅电极的电可擦除可编程非易失性半导体存储器单元布置在 矩阵形式。 在具有三层结构的栅电极中，第一层浮置栅电极通过第一栅极绝缘膜与半导体衬底表面相对，并且第二或第三层栅极用作擦除和控制栅电极之一。 擦除栅电极通过隧道绝缘膜与浮栅的一部分相对，并且控制栅电极通过第二栅极绝缘膜与浮栅电极相对。 擦除和控制栅电极被布置成彼此平行并且垂直于源区和漏区。 在沟道区域的长度方向上彼此相邻的两个单元晶体管中，一个单元晶体管的源极区域与另一个单元晶体管的漏极区域相同，并且在晶体管的宽度方向上彼此相邻的单元晶体管 沟道区域通过形成在沟道区域之间的半导体衬底中的元件隔离区元件隔离。

    Non-volatile semiconductor memory
    67.
    发明授权
    Non-volatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US5034926A

    公开(公告)日：1991-07-23

    申请号：US392070

    申请日：1989-08-10

    申请人： Tadayuki Taura ,  Masamichi Asano ,  Sadayuki Yokoyama

    发明人： Tadayuki Taura ,  Masamichi Asano ,  Sadayuki Yokoyama

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/10 ,  G11C16/16

    CPC分类号： G11C16/16 ,  G11C16/10

    摘要： In a non-volatile semiconductor memory of this invention, a memory cell array constituted by a plurality of memory cells is divided into a plurlaity of blocks, and erase lines which are common to the respective blocks and independent from each other are arranged. In the data write mode, a predetermined voltage is applied to only the erase line connected to a selected one of the blocks.

    摘要翻译： 在本发明的非易失性半导体存储器中，由多个存储单元构成的存储单元阵列被划分为多个块，并且布置了各个块相互独立的擦除线。 在数据写入模式中，只将预定电压施加到连接到所选择的一个块的擦除线。

    Semiconductor memory device with redundancy circuit
    70.
    发明授权
    Semiconductor memory device with redundancy circuit 失效
    具有冗余电路的半导体存储器件

    公开(公告)号：US4858192A

    公开(公告)日：1989-08-15

    申请号：US225510

    申请日：1988-07-28

    申请人： Yuuichi Tatsumi ,  Hidenobu Minagawa ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

    发明人： Yuuichi Tatsumi ,  Hidenobu Minagawa ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

    IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/781

    摘要： A semiconductor memory device has a redundancy circuit for compensating a defective bit when it occurs in the main memory cells. The redundancy circuit includes spare memory cells, a spare row decoder for selecting the spare memory cells, a first circuit section for inhibiting the use of the main row decoder when the spare row decoder is used, and a second circuit section for selecting the spare row decoder when an address specifying the main row line connected to the defective memory cell is denoted.

    摘要翻译： 半导体存储器件具有用于在发生在主存储器单元中时补偿有缺陷的位的冗余电路。 冗余电路包括备用存储单元，用于选择备用存储单元的备用排解码器​​，当使用备用行解码器时禁止使用主行解码器的第一电路部分和用于选择备用行的第二电路部分 解码器，当指定连接到有缺陷的存储单元的主行线的地址被表示时。