公开(公告)号：US09761587B2

公开(公告)日：2017-09-12

申请号：US15344232

申请日：2016-11-04

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/84 ,  H01L27/092 ,  H01L29/165 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8256 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/785

Abstract: A silicon germanium alloy (SiGe) fin having a first germanium content is provided within first and second device regions. Each SiGe fin is located on a sacrificial material stack and an oxide material surrounds each SiGe fin. A germanium layer is formed atop each SiGe fin within one of the device regions, while a SiGe layer having a second germanium content less than the first germanium content is formed atop each SiGe fin within the other device region. An exposed surface of each of the germanium layer and the SiGe layer is then bonded to a base substrate. The sacrificial material stack is removed and thereafter the oxide material is recessed to expose a portion of each SiGe fin in the first and second device regions. Each SiGe fin contacting the germanium layer compressively strained, and each SiGe fin contacting the SiGe layer is tensely strained.

公开(公告)号：US20170236924A1

公开(公告)日：2017-08-17

申请号：US15584851

申请日：2017-05-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC: H01L29/735 ,  H01L21/02

CPC classification number: H01L21/02507 ,  H01L21/8249 ,  H01L29/06 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/155 ,  H01L29/165 ,  H01L29/42304 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/735

Abstract: A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.

公开(公告)号：US20170213884A1

公开(公告)日：2017-07-27

申请号：US15298733

申请日：2016-10-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L49/02 ,  H01L21/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/1087 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28556 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/092 ,  H01L28/40 ,  H01L28/60 ,  H01L28/86 ,  H01L28/90 ,  H01L28/92 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/945

Abstract: An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.

公开(公告)号：US20170194357A1

公开(公告)日：2017-07-06

申请号：US15228141

申请日：2016-08-04

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/308 ,  H01L29/10 ,  H01L27/088 ,  H01L29/66 ,  H01L29/165 ,  H01L29/423

CPC classification number: H01L27/1211 ,  B82Y10/00 ,  H01L21/3081 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/125 ,  H01L29/165 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66818 ,  H01L29/775

Abstract: A threshold voltage tuning approach for forming a stacked nanowire gate-all around pFET is provided. In the present application, selective condensation (i.e., oxidation) is used to provide a threshold voltage shift in silicon germanium alloy nanowires. The threshold voltage shift is well controlled because both underlying parameters which govern the final germanium content, i.e., nanowire width and amount of condensation, are well controlled by the selective condensation process. The present application can address the problem of width quantization in stacked nanowire FETs by offering various device options.

公开(公告)号：US20170186742A1

公开(公告)日：2017-06-29

申请号：US14979939

申请日：2015-12-28

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666

Abstract: A method for fabricating a semiconductor structure is provided that includes the steps of: forming a structure including a substrate, a counter-doped layer on the substrate, and a heavily doped source contact layer on a side of the counter-doped layer opposite the substrate; and forming an oxide layer on a side of the heavily doped source contact layer opposite the counter-doped layer, wherein the oxide layer has a vertical dimension that is a difference between a length of a long channel thick oxide device and a length of a short channel non-thick oxide device.

公开(公告)号：US20170179282A1

公开(公告)日：2017-06-22

申请号：US15297345

申请日：2016-10-19

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A method of making a vertical transistor includes forming a doped source on a substrate; depositing a sacrificial gate material on the source; forming a trench in the sacrificial gate material to expose the doped source; growing an epitaxial layer within the trench to form a channel region extending from the doped source and through the sacrificial gate material; performing an epitaxial growth process to grow an epitaxial layer on a portion of the channel region to form a drain over the sacrificial gate material; depositing a dielectric material on the drain to form a spacer that protects the epitaxial growth; and removing the sacrificial gate material and replacing the sacrificial gate material with a gate stack that surrounds the channel region between the doped source and the drain.

公开(公告)号：US20170179128A1

公开(公告)日：2017-06-22

申请号：US15257073

申请日：2016-09-06

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/092 ,  H01L29/04 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545

Abstract: A semiconductor structure is provided that includes a substrate comprising a first semiconductor material having a first crystallographic orientation and a first device region and a second device region. First vertically stacked and suspended nanosheets of semiconductor channel material of the first crystallographic orientation are located above the substrate and within the first device region. Second vertically stacked and suspended nanosheets of semiconductor channel material of a second crystallographic orientation are located above the substrate and within the second device region. In accordance with the present application, the second crystallographic orientation is different from the first crystallographic orientation.

公开(公告)号：US09684753B2

公开(公告)日：2017-06-20

申请号：US14299496

申请日：2014-06-09

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Josephine B. Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

IPC: G06F17/50 ,  H01L29/06 ,  H01L21/84

CPC classification number: G06F17/5068 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/84 ,  H01L29/0669

Abstract: In one aspect, a CAD-based method for designing a lithographic mask for nanowire-based devices is provided which includes the steps of: create a design for the mask from existing (e.g., FINFET or planar CMOS) design data which includes, for each of the devices, one or more nanowire mask shapes (FINFET design data) or continuous shapes (planar CMOS design data); for FINFET design data, merging the nanowire mask shapes into continuous shapes; expanding the continuous shapes to join all of the continuous shapes in the design together forming a single polygon shape; removing the continuous shapes from the single polygon shape resulting in landing pad shapes for anchoring the nanowire mask shapes; for CMOS design data, dividing the continuous active shapes into one or more nanowire mask shapes; and merging the landing pad shapes with the nanowire mask shapes to form the lithographic mask.

公开(公告)号：US09653289B1

公开(公告)日：2017-05-16

申请号：US15268993

申请日：2016-09-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/336 ,  H01L21/00 ,  H01L21/338 ,  H01L21/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/311 ,  H01L21/308 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/42376 ,  H01L21/02603 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78651 ,  H01L29/78696

Abstract: A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.

公开(公告)号：US09627267B2

公开(公告)日：2017-04-18

申请号：US15144136

申请日：2016-05-02

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/00 ,  H01L21/8238 ,  H01L29/165 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/7849

Abstract: A method includes forming a set of fins composed of a first semiconductor material. The method further heats the set of fins to condense the fins and cause growth of a layer of oxide on vertical sidewalls thereof, masking a first sub-set of the fins, forming a plurality of voids in the oxide by removing a second sub-set of fins, where each void has a three-dimensional shape and dimensions that correspond to a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set, and epitaxially growing in the voids a third sub-set of fins. The third sub-set of fins is composed of a second semiconductor material that differs from the first semiconductor material. Each fin of the third subset has a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set. At least one structure formed by the method is also disclosed.