公开(公告)号：US10141529B1

公开(公告)日：2018-11-27

申请号：US15813526

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Damon B. Farmer ,  Shu-Jen Han ,  Jianshi Tang ,  John J. Yurkas

IPC: H01L29/06 ,  H01L51/10 ,  H01L51/05 ,  H01L51/00

CPC classification number: H01L51/105 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/0566 ,  H01L2251/301

Abstract: Embodiments of the invention are directed to methods and resulting structures for enhancing drive current and increasing device yield in n-type carbon nanotube field effect transistors (CNT FETs) with scaled contacts using a wetting layer. In some embodiments of the invention, a nanotube is formed over a surface of a substrate. An insulating layer is formed over the nanotube such that end portions of the nanotube are exposed. A low work function metal is formed over the end portions of the nanotube and a wetting layer is formed between the low work function metal and the nanotube.

公开(公告)号：US10050167B2

公开(公告)日：2018-08-14

申请号：US15179109

申请日：2016-06-10

Applicant: International Business Machines Corporation

Inventor： Qing Cao ,  Shu-Jen Han ,  Li-Wen Hung

IPC: H01L23/00 ,  H01L31/02 ,  H01L31/105 ,  H01L31/0203 ,  G06K19/073 ,  G06K7/10 ,  H01L31/075 ,  H01L31/0288 ,  H01L31/18 ,  B81C1/00 ,  H01L31/05 ,  H01L23/544

Abstract: Embodiments relate to the detection of semiconductor tampering with a light-sensitive circuit. A tamper detection device for an integrated circuit includes a light-sensitive circuit disposed within a package of an integrated circuit. The light-sensitive circuit closes in response to an exposure to a light source, indicating a tamper condition.

公开(公告)号：US09972800B2

公开(公告)日：2018-05-15

申请号：US15383670

申请日：2016-12-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shu-Jen Han ,  Jianshi Tang

IPC: H01L51/10 ,  H01L51/05 ,  H01L51/00

CPC classification number: H01L51/105 ,  H01L51/002 ,  H01L51/0021 ,  H01L51/0023 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/0558 ,  H01L51/107 ,  H01L2251/301

Abstract: A field effect transistor includes a substrate and a gate dielectric formed on the substrate. A channel material is formed on the dielectric layer. The channel material includes carbon nanotubes. A patterned resist layer has openings formed therein. Metal contacts are formed on the channel material in the openings in the patterned resist layer and over portions of the patterned resist layer to protect sidewalls of the metal contacts to prevent degradation of the metal contacts.

公开(公告)号：US20170244054A1

公开(公告)日：2017-08-24

申请号：US15046723

申请日：2016-02-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sarunya Bangsaruntip ,  Michael Engel ,  Shu-Jen Han

IPC: H01L51/05 ,  H01L29/423 ,  H01L51/00 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0669 ,  H01L21/02623 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/1606 ,  H01L29/42376 ,  H01L29/66045 ,  H01L29/66477 ,  H01L29/66553 ,  H01L29/778 ,  H01L29/78 ,  H01L51/0048 ,  H01L51/0541 ,  H01L51/057

Abstract: A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.

公开(公告)号：US09704965B1

公开(公告)日：2017-07-11

申请号：US15277291

申请日：2016-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Cao ,  Shu-Jen Han ,  Ning Li ,  Jianshi Tang

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/265 ,  H01L29/08 ,  H01L29/78 ,  H01L21/3205

CPC classification number: H01L21/2807 ,  B82Y10/00 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/32056 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

公开(公告)号：US20170133609A1

公开(公告)日：2017-05-11

申请号：US14933339

申请日：2015-11-05

Applicant: International Business Machines Corporation

Inventor： Qing Cao ,  Shu-Jen Han ,  Jianshi Tang

IPC: H01L51/10 ,  H01L51/05

CPC classification number: H01L51/105 ,  H01L51/0021 ,  H01L51/0026 ,  H01L51/0048 ,  H01L51/0558 ,  H01L2251/301

Abstract: A method of forming an end-bonded contact on a semiconductor is disclosed herein. The method can include forming a dielectric layer on a substrate and depositing a carbon nanotube layer onto the dielectric layer. Additionally, the method can include depositing a resist mask onto the carbon nanotube layer and patterning the resist mask to form a contact mold such that a portion of the carbon nanotube layer is exposed. In some aspects, the method can include depositing a contact metal such that the contact metal contacts the exposed carbon nanotube layer and thermally annealing the device such that the carbon nanotube layer dissolves into the contact metal such that a single contact surface is formed between the contact and the carbon nanotube layer.

公开(公告)号：US20170125709A1

公开(公告)日：2017-05-04

申请号：US15207938

申请日：2016-07-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shu-Jen Han ,  Jianshi Tang

IPC: H01L51/05 ,  H01L51/10 ,  H01L51/00

CPC classification number: H01L51/105 ,  H01L51/002 ,  H01L51/0021 ,  H01L51/0023 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/0558 ,  H01L51/107 ,  H01L2251/301

Abstract: A field effect transistor includes a substrate and a gate dielectric formed on the substrate. A channel material is formed on the dielectric layer. The channel material includes carbon nanotubes. A patterned resist layer has openings formed therein. Metal contacts are formed on the channel material in the openings in the patterned resist layer and over portions of the patterned resist layer to protect sidewalls of the metal contacts to prevent degradation of the metal contacts.

公开(公告)号：US09525147B2

公开(公告)日：2016-12-20

申请号：US14615554

申请日：2015-02-06

Applicant: International Business Machines Corporation

Inventor： Qing Cao ,  Kangguo Cheng ,  Shu-Jen Han ,  Zhengwen Li ,  Fei Liu

IPC: H01L21/44 ,  H01L51/05 ,  H01L51/00 ,  H01L27/28 ,  H01L51/10

CPC classification number: H01L51/0545 ,  H01L27/283 ,  H01L51/0006 ,  H01L51/0017 ,  H01L51/0021 ,  H01L51/0048 ,  H01L51/055 ,  H01L51/0558 ,  H01L51/105

Abstract: A method of arranging at least one carbon nanotube on a semiconductor substrate includes depositing the at least one carbon nanotube on a dielectric layer of the semiconductor device. The method further includes arranging the at least one carbon nanotube on the dielectric layer in response to applying a voltage potential to an electrically conductive electrode of the semiconductor device, and applying a ground potential to an electrically conductive semiconductor layer of the semiconductor device.

Abstract translation: 在半导体衬底上配置至少一个碳纳米管的方法包括在半导体器件的电介质层上沉积至少一个碳纳米管。 该方法还包括响应于向半导体器件的导电电极施加电压电位并将电位施加到半导体器件的导电半导体层，将介电层上的至少一个碳纳米管布置在电介质层上。

公开(公告)号：US09515216B2

公开(公告)日：2016-12-06

申请号：US14744171

申请日：2015-06-19

Applicant: International Business Machines Corporation

Inventor： Qing Cao ,  Shu-Jen Han ,  Li-Wen Hung

IPC: H01L31/075 ,  H01L31/18 ,  H01L31/05 ,  B81C1/00

CPC classification number: H01L31/075 ,  B81C1/0015 ,  G06K7/10366 ,  G06K19/07372 ,  H01L23/544 ,  H01L23/576 ,  H01L31/02005 ,  H01L31/02019 ,  H01L31/0203 ,  H01L31/0288 ,  H01L31/05 ,  H01L31/105 ,  H01L31/1804 ,  H01L2223/5444 ,  H01L2223/54486 ,  H01L2924/14

Abstract: Embodiments relate to the detection of semiconductor tampering with a light-sensitive circuit. A tamper detection device for an integrated circuit includes a light-sensitive circuit disposed within a package of an integrated circuit. The light-sensitive circuit closes in response to an exposure to a light source, indicating a tamper condition.

公开(公告)号：US20160322314A1

公开(公告)日：2016-11-03

申请号：US15179109

申请日：2016-06-10

Applicant: International Business Machines Corporation

Inventor： Qing Cao ,  Shu-Jen Han ,  Li-Wen Hung

IPC: H01L23/00 ,  G06K7/10 ,  H01L31/105 ,  G06K19/073 ,  H01L31/02 ,  H01L31/0203

CPC classification number: H01L31/075 ,  B81C1/0015 ,  G06K7/10366 ,  G06K19/07372 ,  H01L23/544 ,  H01L23/576 ,  H01L31/02005 ,  H01L31/02019 ,  H01L31/0203 ,  H01L31/0288 ,  H01L31/05 ,  H01L31/105 ,  H01L31/1804 ,  H01L2223/5444 ,  H01L2223/54486 ,  H01L2924/14

Abstract: Embodiments relate to the detection of semiconductor tampering with a light-sensitive circuit. A tamper detection device for an integrated circuit includes a light-sensitive circuit disposed within a package of an integrated circuit. The light-sensitive circuit closes in response to an exposure to a light source, indicating a tamper condition.