公开(公告)号：US20240120305A1

公开(公告)日：2024-04-11

申请号：US17938784

申请日：2022-10-07

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram ,  Mohammad Mamunur Rahman

IPC: H01L23/00 ,  H01L23/538

CPC classification number: H01L24/16 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/14 ,  H01L24/32 ,  H01L24/73 ,  H01L24/13 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13686 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of a microelectronic assembly includes: a package substrate and an integrated circuit (IC) die coupled to a surface of the package substrate by first interconnects and second interconnects, the first interconnects and the second interconnects comprising solder. The first interconnects are larger than the second interconnects, the first interconnects and the second interconnects further comprise bumps on the IC die and bond-pads on the surface of the package substrate, with the solder coupled to the bumps and the bond-pads, lateral sides of the bumps have a coating of a material that prevents solder wicking, and the surface of the package substrate includes insulative baffles between the bond-pads.

公开(公告)号：US20240113158A1

公开(公告)日：2024-04-04

申请号：US17957003

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon C. Marin ,  Haobo Chen ,  Changhua Liu ,  Srinivas Venkata Ramanuja Pietambaram

IPC: H01L49/02 ,  H01L25/16

CPC classification number: H01L28/91 ,  H01L25/16 ,  H01L28/92

Abstract: Disclosed herein are microelectronics package architectures utilizing in-situ high surface area capacitor in substrate packages and methods of manufacturing the same. The substrates may include an anode material, a cathode material, and a conductive material. The anode material may have an anode surface that may define a plurality of anode peaks and anode valleys. The cathode material may have a cathode surface that may define a plurality of cathode peaks and cathode valleys complementary to the plurality of anode peaks and anode valleys. The conductive material may be located at the anode peaks.

公开(公告)号：US20240113047A1

公开(公告)日：2024-04-04

申请号：US17957225

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Srinivasan Raman ,  Brandon C. Marin ,  Suddhasattwa Nad ,  Gang Duan ,  Benjamin Duong ,  Srinivas Venkata Ramanuja Pietambaram ,  Kripa Chauhan

IPC: H01L23/64

CPC classification number: H01L23/647 ,  H01L21/31105

Abstract: Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.

公开(公告)号：US20240006299A1

公开(公告)日：2024-01-04

申请号：US17855568

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Jason Steill ,  Yi Yang ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Marcel Arlan Wall ,  Gang Duan ,  Jeremy D. Ecton

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49833 ,  H01L23/49822 ,  H01L21/4857

Abstract: Disclosed herein are microelectronics package architectures utilizing SiNx based surface finishes and methods of manufacturing the same. The microelectronics packages may include a core material, a first plurality of pads, and a silicon nitride layer. The first plurality of pads are attached to the core material. The silicon nitride layer is attached to the core material. The silicon nitride material defines respective openings to expose at least a portion of each of the first plurality of pads.

公开(公告)号：US20230345621A1

公开(公告)日：2023-10-26

申请号：US18344944

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Andrew James Brown ,  Rahul Jain ,  Dilan Seneviratne ,  Praneeth Kumar Akkinepally ,  Frank Truong

IPC: H05K1/02 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0228 ,  H01L23/49822 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/111 ,  H05K1/181

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a dielectric layer, in a substrate, the dielectric layer including an electroless catalyst, wherein the electroless catalyst includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, and tantalum; a first conductive trace having a first thickness in the dielectric layer, wherein the first thickness is between 4 um and 143 um; and a second conductive trace having a second thickness in the dielectric layer, wherein the second thickness is between 2 um and 141 um, wherein the first thickness is greater than the second thickness, and wherein the first conductive trace and the second conductive trace have sloped sidewalls.

公开(公告)号：US11721650B2

公开(公告)日：2023-08-08

申请号：US16437930

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Aleksandar Aleksov ,  Georgios Dogiamis ,  Jeremy D. Ecton ,  Suddhasattwa Nad ,  Mohammad Mamunur Rahman

IPC: H01L23/66 ,  H01L23/498 ,  H01L21/48 ,  H01P3/08 ,  H01P11/00 ,  H01P3/06

CPC classification number: H01L23/66 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49838 ,  H01P3/06 ,  H01P3/08 ,  H01P3/088 ,  H01P11/003 ,  H01P11/005 ,  H01L2223/6627

Abstract: Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes first waveguides over a package substrate. The first waveguides include first angled conductive layers, first transmission lines, and first cavities. The semiconductor package also includes a first dielectric over the first waveguides and package substrate, second waveguides over the first dielectric and first waveguides, and a second dielectric over the second waveguides and first dielectric. The second waveguides include second angled conductive layers, second transmission lines, and second cavities. The first angled conductive layers are positioned over the first transmission lines and package substrate having a first pattern of first triangular structures. The second angled conductive layers are positioned over the second transmission lines and first dielectric having a second pattern of second triangular structures, where the second pattern is shaped as a coaxial interconnects enclosed with second triangular structures and portions of first dielectric.

公开(公告)号：US20230163047A1

公开(公告)日：2023-05-25

申请号：US17531459

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Brandon C. Marin

IPC: H01L23/427

CPC classification number: H01L23/4275

Abstract: A package substrate, upon which integrated circuit device(s) of an integrated circuit assembly are electrically attached, may include at least one internal fluid conduit that allows for a heat transfer fluid of the two-phase immersion system to transfer heat within the integrated circuit assembly. The at least one internal fluid conduit may comprise at least one fluid channel formed within the package substrate and at least one fluid port extending from an external surface of the package substrate to the at least one fluid channel. The at least one fluid channel may be formed within the package substrate during the formation thereof, then, after the formation of the package substrate, the fluid channels may be “opened” by forming the at least one fluid port.

公开(公告)号：US20230092492A1

公开(公告)日：2023-03-23

申请号：US17480064

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Xin Ning ,  Brandon C. Marin ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Numair Ahmed ,  Brent Williams ,  Mollie Stewart ,  Nathan Ou ,  Cary Kuliasha

IPC: H01L23/64 ,  H01F27/28 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48

Abstract: Transmission pathways in substrates, and associated methods are shown. Example transmission pathways include a semiconductor substrate with a core, a dielectric layer fixed on the core, at least one first electrical transmission pathway extending through at least one of the dielectric layer and the core. The first pathway includes a magnetic material disposed within the at least the core of the at least one first electrical transmission pathway, at least one second electrical transmission pathway extending through the magnetic material, a nickel layer disposed on inner circumferential surface of the magnetic material at least within the second electrical transmission pathway, a copper layer disposed on at least the nickel layer within the second electrical transmission pathway. The dielectric spacer or the nickel layer separates the copper layer from the magnetic material. At least one third pathway extends through at least one of the dielectric layer and the core separate from the at least one electrical transmission pathway.

公开(公告)号：US11605867B2

公开(公告)日：2023-03-14

申请号：US17344715

申请日：2021-06-10

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Jeremy D. Ecton ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Yonggang Li ,  Dilan Seneviratne

IPC: H01P1/208 ,  H01P1/20 ,  H01P7/10 ,  H01L23/66 ,  H01P3/16 ,  H01L21/768 ,  H01P11/00 ,  H01L21/288

Abstract: A method of fabricating an RF filter on a semiconductor package comprises forming a first dielectric buildup film. A second dielectric buildup film is formed over the first dielectric buildup film, the second dielectric buildup film comprising a dielectric material that contains a metallization catalyst, wherein the dielectric material comprises one of an epoxy-polymer blend dielectric material, silicon dioxide and silicon nitride, and a low-k dielectric. A trench is formed in the second dielectric buildup film with laser ablation, wherein the laser ablation selectively activates sidewalls of the trench for electroless metal deposition. A metal selectively is plated to sidewalls of the trench based at least in part on the metallization catalyst and immersion in an electroless solution. A low-loss buildup film is formed over the metal that substantially fills the trench.

公开(公告)号：US20230071707A1

公开(公告)日：2023-03-09

申请号：US17470588

申请日：2021-09-09

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Brandon C. Marin ,  Kristof Darmawikarta ,  Srinivas Venkata Ramanuja Pietambaram

IPC: G02F1/035

Abstract: An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.