公开(公告)号：US06699783B2

公开(公告)日：2004-03-02

申请号：US10303355

申请日：2002-11-21

Applicant: Ivo Raaijmakers ,  Pekka T. Soininen ,  Ernst H. A. Granneman ,  Suvi P. Haukka

Inventor： Ivo Raaijmakers ,  Pekka T. Soininen ,  Ernst H. A. Granneman ,  Suvi P. Haukka

IPC: H01L214763

CPC classification number: C23C16/045 ,  C23C16/45525 ,  H01L21/28562 ,  H01L21/32051 ,  H01L21/7681 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.

Abstract translation: 提供了用于集成电路中的双镶嵌结构的保形衬里的方法和结构，特别是在多孔材料中形成的开口。 沟槽和接触通孔形成在绝缘层中。 沟槽和通孔的侧壁上的孔堵塞，然后将结构暴露于交替的化学物质以形成所需衬里材料的单层。 在示例性工艺流程中，密封层的化学或物理气相沉积（CVD或PVD）由于不完全的一致性而阻塞孔，并且之后是原子层沉积（ALD），特别是交替脉冲的金属卤化物和注入恒定的氨气 载体流。 交替的方法也可以布置成在绝缘体的孔内以CVD模式起作用，因为反应物不容易从脉冲之间的孔中吹扫。 自身端接的金属层因此与氮气反应。 接近完美的台阶覆盖允许扩散阻挡功能的最小厚度，从而使任何给定沟槽和通孔尺寸的后续填充金属的体积最大化。

公开(公告)号：US06596973B1

公开(公告)日：2003-07-22

申请号：US10096138

申请日：2002-03-07

Applicant: James J. Donald ,  Ivo Raaijmakers

Inventor： James J. Donald ,  Ivo Raaijmakers

IPC: F27B514

CPC classification number: H01L21/67248 ,  C30B25/16

Abstract: A wafer temperature estimator calibrates contact-type temperature sensor measurements that are used by a temperature controller to control substrate temperature in a high temperature processing chamber. Wafer temperature estimator parameters provide an estimated wafer temperature from contact-type temperature sensor measurements. The estimator parameters are refined using non-contact-type temperature sensor measurements during periods when the substrate temperature is decreasing or the heaters are off. A corresponding temperature control system includes a heater, a contact-type temperature sensor in close proximity to the substrate, and an optical pyrometer placed to read temperature directly from the substrate. A wafer temperature estimator uses the estimator parameters and measurements from the contact-type sensor to determine an estimated wafer temperature. A temperature controller reads the estimated wafer temperature and makes changes to the heater power accordingly. The wafer temperature estimator has a nonlinear neural network system that is trained using inputs from the various sensors.

Abstract translation: 晶片温度估计器校准由温度控制器用于控制高温处理室中的衬底温度的接触式温度传感器测量。 晶圆温度估计器参数提供来自接触式温度传感器测量值的估计晶片温度。 在衬底温度降低或加热器关闭的期间，使用非接触式温度传感器测量来精确估算器参数。 相应的温度控制系统包括加热器，靠近基板的接触式温度传感器和放置以直接从基板读取温度的光学高温计。 晶片温度估计器使用来自接触型传感器的估计器参数和测量来确定估计的晶片温度。 温度控制器读取估计的晶片温度并相应地改变加热器功率。 晶片温度估计器具有使用来自各种传感器的输入进行训练的非线性神经网络系统。

公开(公告)号：US06534395B2

公开(公告)日：2003-03-18

申请号：US09800757

申请日：2001-03-06

Applicant: Christiaan J. Werkhoven ,  Ivo Raaijmakers ,  Suvi P. Haukka

Inventor： Christiaan J. Werkhoven ,  Ivo Raaijmakers ,  Suvi P. Haukka

IPC: H01L214763

CPC classification number: H01L21/28185 ,  C23C16/029 ,  C23C16/34 ,  C23C16/401 ,  C23C16/403 ,  C23C16/405 ,  C23C16/452 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45534 ,  C30B25/14 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3162 ,  H01L21/31641 ,  H01L21/3185 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76879 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2221/1089 ,  H01L2924/0002 ,  Y10T428/24942 ,  Y10T428/2495 ,  H01L2924/00

Abstract: Thin films are formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a graded transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.

Abstract translation: 通过原子层沉积形成薄膜，由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变化到单层。 在所示实施例中，在循环过程中引入了不同量的杂质源。 因此，即使对于非常薄的层也提供了梯度栅极电介质。 薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。 类似地，栅极电介质可以从氧化铝变化为氧化铝和较高电介质材料（例如，ZrO 2）到纯高k材料并返回到氧化铝的混合物。 在另一个实施例中，金属氮化物（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。 在交替沉积过程中，铜可以被引入，例如分开的脉冲，并且铜源脉冲可以逐渐增加频率，形成渐变过渡区，直到在上表面形成纯铜。 有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。

公开(公告)号：US06511539B1

公开(公告)日：2003-01-28

申请号：US09392371

申请日：1999-09-08

Applicant: Ivo Raaijmakers

Inventor： Ivo Raaijmakers

IPC: C30B2514

CPC classification number: C23C16/45544 ,  C23C16/452 ,  C23C16/45521 ,  C23C16/45536 ,  C23C16/45542 ,  C30B25/14 ,  C30B29/38 ,  H01J37/3244 ,  Y10T117/10

Abstract: An improved apparatus and method for substrate layer deposition in which substrate layers are grown by carrier gas delivery of sequential pulses of reactants to the substrate surface. At least one of the reactants comprises excited species, e.g., radicals. In a specific embodiment, the apparatus of this invention provides sequential repeated pulses of reactants in a flow of carrier gas for reaction at a substrate surface. The reactant pulses are delivered with sufficient intervening delay times to minimize undesirable reaction between reactants in adjacent pulses in the gas phase or undesired uncontrolled reactions on the substrate surface.

Abstract translation: 一种用于衬底层沉积的改进的装置和方法，其中衬底层通过将反应物的顺序脉冲的载气输送到衬底表面而生长。 至少一种反应物包括激发的物质，例如自由基。 在具体实施方案中，本发明的装置在载体气流中提供反应物的顺序重复脉冲，以在基底表面反应。 反应物脉冲以足够的中间延迟时间递送，以使气相中相邻脉冲中的反应物之间的不希望的反应最小化，或者在衬底表面上产生不期望的不受控制的反应。

公开(公告)号：US06242718B1

公开(公告)日：2001-06-05

申请号：US09434030

申请日：1999-11-04

Applicant: Armand Ferro ,  Ivo Raaijmakers ,  Ravinder Aggarwal ,  Ronald R. Stevens

Inventor： Armand Ferro ,  Ivo Raaijmakers ,  Ravinder Aggarwal ,  Ronald R. Stevens

IPC: A21B100

CPC classification number: H01L21/6835 ,  H01L21/6838 ,  H01L2221/68359 ,  Y10S414/135

Abstract: A Bernoulli wand type semiconductor wafer pickup device that is adapted to regulate the temperature of a wafer while the wafer is being repositioned within a semiconductor processing system. In one embodiment, the device is comprised of a resistive heating element that is adapted to raise the temperature of the pickup device. In particular, by raising the temperature of the pickup device, a portion of the thermal radiation emitted from the device is absorbed by the wafer, thus providing a means for regulating the wafer temperature. In another embodiment, the device is adapted with the characteristics of a black body absorber so as to enable the device to optimally absorb thermal radiation from external radiant sources, thereby providing a means for increasing the temperature of the device. In another embodiment, the device is coated with reflective material that enables a large portion of thermal radiation emitted from the wafer to be reflected and absorbed back into the wafer. In another embodiment, the preexisting gas system of the pickup device is adapted with a gas beating device that is adapted to raise the temperature of the gas so as to regulate the temperature of the wafer.

Abstract translation: 一种伯努利棒状半导体晶片拾取装置，其适于在晶片在半导体处理系统内重新定位时调节晶片的温度。 在一个实施例中，该装置包括适于提升拾取装置的温度的电阻加热元件。 特别地，通过提高拾取装置的温度，从装置发射的热辐射的一部分被晶片吸收，从而提供调节晶片温度的装置。 在另一个实施例中，该装置适于具有黑体吸收体的特征，以便能够使装置最佳地吸收来自外部辐射源的热辐射，由此提供用于增加装置温度的装置。 在另一个实施例中，该装置涂覆有反射材料，其使得能够将从晶片发射的大部分热辐射反射并吸收回到晶片中。 在另一个实施例中，拾取装置的预先存在的气体系统适用于气体打浆装置，该气体打浆装置适于升高气体的温度以调节晶片的温度。

公开(公告)号：US6113698A

公开(公告)日：2000-09-05

申请号：US889990

申请日：1997-07-10

Applicant: Ivo Raaijmakers ,  Dan Marohl

Inventor： Ivo Raaijmakers ,  Dan Marohl

IPC: C23C16/02 ,  C23C16/44 ,  C23C16/455 ,  H01L21/00 ,  H01L21/683 ,  C23C16/00

CPC classification number: C23C16/45521 ,  C23C16/0209 ,  C23C16/0227 ,  H01L21/67103 ,  H01L21/6838

Abstract: An apparatus and method for clamping and heating a wafer without using moving parts and without exposing the wafer to external stress is provided. A high backside wafer pressure which provides efficient heat transfer from a heated substrate support to the wafer is offset by a high frontside wafer pressure higher than or lower than the backside wafer pressure. The high frontside pressure reduces wafer stress by providing a uniform frontside/backside pressure and presses the wafer against the heated substrate support. A continuous gas purge for providing a viscous flow across the wafer to carry away desorbed contaminants, and frontside heating elements for improving desorption are provided.

Abstract translation: 提供一种用于在不使用移动部件并且不使晶片暴露于外部应力的情况下夹紧和加热晶片的装置和方法。 提供从加热的衬底支撑件到晶片的有效热传递的高背面晶片压力被高于或低于后侧晶片压力的高前侧晶片压力抵消。 高前端压力通过提供均匀的前侧/后侧压力来降低晶片应力，并将晶片压靠在加热的基板支撑件上。 提供连续的气体吹扫，用于提供穿过晶片的粘性流以携带脱附的污染物，以及用于改善解吸的前侧加热元件。

公开(公告)号：US08343583B2

公开(公告)日：2013-01-01

申请号：US12498885

申请日：2009-07-07

Applicant: Gert Jan Snijders ,  Ivo Raaijmakers

Inventor： Gert Jan Snijders ,  Ivo Raaijmakers

IPC: C23C16/442

CPC classification number: C23C16/4481

Abstract: Methods and systems for depositing a film on a substrate are disclosed. In one embodiment, a method includes converting a non-gaseous precursor into vapor phase. Converting the precursor includes: forming a fluidized bed by flowing gas at a sufficiently high flow rate to suspend and stir a plurality of solid particles, and converting the phase of the non-gaseous precursor into vapor phase in the fluidized bed. The method also includes transferring the precursor in vapor phase through a passage; and performing deposition on one or more substrates with the transferred precursor in vapor phase.

Abstract translation: 公开了在衬底上沉积膜的方法和系统。 在一个实施方案中，一种方法包括将非气态前体转化成气相。 转化前体包括：通过以足够高的流速流动气体来形成流化床以悬浮和搅拌多个固体颗粒，并将非气态前体的相转化为流化床中的气相。 该方法还包括将气相中的前体转移通过通道; 并且在一个或多个基底上进行沉积，转移的前体在气相中。

公开(公告)号：US08317921B2

公开(公告)日：2012-11-27

申请号：US11124329

申请日：2005-05-06

Applicant: Armand Ferro ,  Ivo Raaijmakers ,  Derrick Foster

Inventor： Armand Ferro ,  Ivo Raaijmakers ,  Derrick Foster

IPC: C23C16/52 ,  C23C16/455 ,  C23F1/00 ,  H01L21/306 ,  C23C16/06 ,  C23C16/22

CPC classification number: C30B29/06 ,  C23C16/4405 ,  C23C16/481 ,  C30B25/02 ,  C30B25/105 ,  C30B25/14 ,  C30B33/005 ,  C30B33/02 ,  C30B33/12 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02301 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/28017 ,  H01L21/31116 ,  H01L21/31612 ,  H01L21/31662 ,  H01L29/66651

Abstract: A single-wafer, chemical vapor deposition reactor is provided with hydrogen and silicon source gas suitable for epitaxial silicon deposition, as well as a safe mixture of oxygen in a non-reactive gas. Methods are provided for forming oxide and silicon layers within the same chamber. In particular, a sacrificial oxidation is performed, followed by a hydrogen bake to sublime the oxide and leave a clean substrate. Epitaxial deposition can follow in situ. A protective oxide can also be formed over the epitaxial layer within the same chamber, preventing contamination of the critical epitaxial layer. Alternatively, the oxide layer can serve as the gate dielectric, and a polysilicon gate layer can be formed in situ over the oxide.

Abstract translation: 单晶片化学气相沉积反应器具有适用于外延硅沉积的氢和硅源气体，以及非反应性气体中的氧的安全混合物。 提供了在相同的室内形成氧化物层和硅层的方法。 特别地，进行牺牲氧化，然后进行氢气烘烤以使氧化物升华并留下清洁的基材。 外延沉积可以原位追踪。 也可以在同一室内的外延层上形成保护性氧化物，防止关键外延层的污染。 或者，氧化物层可以用作栅极电介质，并且可以在氧化物上原位形成多晶硅栅极层。

公开(公告)号：US08293597B2

公开(公告)日：2012-10-23

申请号：US13084341

申请日：2011-04-11

Applicant: Ivo Raaijmakers

Inventor： Ivo Raaijmakers

IPC: H01L21/8238

CPC classification number: H01L21/76823 ,  C23C16/405 ,  C23C16/56 ,  H01L21/28518 ,  H01L21/28562 ,  H01L29/665 ,  H01L29/66568

Abstract: A method of self-aligned silicidation on structures having high aspect ratios involves depositing a metal oxide film using atomic layer deposition (ALD) and converting the metal oxide film to metal film in order to obtain uniform step coverage. The substrate is then annealed such that the metal in regions directly overlying the patterned and exposed silicon reacts with the silicon to form uniform metal silicide at the desired locations.

Abstract translation: 在具有高纵横比的结构上的自对准硅化物的方法包括使用原子层沉积（ALD）沉积金属氧化物膜并将金属氧化物膜转化为金属膜以获得均匀的台阶覆盖。 然后将衬底退火，使得直接覆盖图案化和暴露的硅的区域中的金属与硅反应，以在期望的位置形成均匀的金属硅化物。

公开(公告)号：US07981791B2

公开(公告)日：2011-07-19

申请号：US12202132

申请日：2008-08-29

Applicant: Suvi P. Haukka ,  Ivo Raaijmakers ,  Wei Min Li ,  Juhana Kostamo ,  Hessel Sprey ,  Christiaan J. Werkhoven

Inventor： Suvi P. Haukka ,  Ivo Raaijmakers ,  Wei Min Li ,  Juhana Kostamo ,  Hessel Sprey ,  Christiaan J. Werkhoven

IPC: H01L21/4763

CPC classification number: C23C16/029 ,  C23C16/34 ,  C23C16/401 ,  C23C16/403 ,  C23C16/405 ,  C23C16/452 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45534 ,  C30B25/14 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3162 ,  H01L21/31641 ,  H01L21/3185 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76879 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2221/1089

Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.

Abstract translation: 通过原子层沉积形成薄膜，由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。 在所示实施例中，在循环过程中引入了不同量的杂质源。 因此，即使对于非常薄的层也提供了梯度栅极电介质。 薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。 类似地，栅极电介质可以从氧化铝变化为氧化铝和较高电介质材料（例如，ZrO 2）到纯高k材料并返回到氧化铝的混合物。 在另一个实施例中，金属氮化物（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。 在交替沉积工艺期间，铜可以被引入，例如分开的脉冲，并且铜源脉冲可以逐渐增加频率，形成过渡区域，直到在上表面形成纯铜。 有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。 在一些实施例中，提供了额外的种子层或附加的过渡层。