公开(公告)号：US20120024230A1

公开(公告)日：2012-02-02

申请号：US13253829

申请日：2011-10-05

申请人： Shijian Li ,  Fritz Redeker ,  Yezdi Dordi

发明人： Shijian Li ,  Fritz Redeker ,  Yezdi Dordi

IPC分类号： H01L21/70 ,  B25B11/00 ,  C23C16/50 ,  C23C16/44 ,  C23C16/458

CPC分类号： H01L21/70 ,  C23C16/045 ,  C23C16/4586 ,  H01L21/67017 ,  H01L21/677 ,  H01L21/6838 ,  H01L21/68714 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T24/44 ,  H01L2924/00012 ,  H01L2924/00

摘要： The present invention pertains to methods, apparatuses, and systems for fabricating three-dimensional integrated circuits. One or more embodiments of systems, apparatuses, and/or methods according to the present invention are presented.

摘要翻译： 本发明涉及用于制造三维集成电路的方法，装置和系统。 呈现了根据本发明的系统，装置和/或方法的一个或多个实施例。

公开(公告)号：US07863179B2

公开(公告)日：2011-01-04

申请号：US11591310

申请日：2006-10-31

申请人： Hyungsuk Alexander Yoon ,  Fritz Redeker

发明人： Hyungsuk Alexander Yoon ,  Fritz Redeker

IPC分类号： H01L21/4763

CPC分类号： H01L21/28562 ,  C23C16/029 ,  C23C16/34 ,  C23C16/45529 ,  H01L21/02183 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/3141 ,  H01L21/318 ,  H01L21/76843 ,  H01L21/76846

摘要： Various embodiments provide improved processes and systems that produce a barrier layer with decreasing nitrogen concentration with the increase of film thickness. A barrier layer with decreasing nitrogen concentration with film thickness allows the end of barrier layer with high nitrogen concentration to have good adhesion with a dielectric layer and the end of barrier layer with low nitrogen concentration (or metal-rich) to have good adhesion with copper. An exemplary method of depositing a barrier layer on an interconnect structure is provided. The method includes (a) providing an atomic layer deposition environment, (b) depositing a barrier layer on the interconnect structure with a first nitrogen concentration during a first phase of deposition in the atomic layer deposition environment. The method further includes (c) continuing the deposition of the barrier layer on the interconnect structure with a second nitrogen concentration during a second phase deposition in the atomic layer deposition environment.

摘要翻译： 各种实施方案提供改进的方法和系统，其随着膜厚度的增加产生具有降低的氮浓度的阻挡层。 具有降低氮浓度的膜厚度的阻挡层允许具有高氮浓度的阻挡层的端部与电介质层和低氮浓度（或富含金属）的阻挡层的端部具有良好的粘附性以与铜具有良好的粘合性 。 提供了在互连结构上沉积阻挡层的示例性方法。 该方法包括（a）提供原子层沉积环境，（b）在原子层沉积环境中的第一沉积阶段期间，在互连结构上沉积具有第一氮浓度的势垒层。 该方法还包括（c）在原子层沉积环境中的第二相沉积期间，继续在互连结构上以第二氮浓度沉积阻挡层。

公开(公告)号：US20100267229A1

公开(公告)日：2010-10-21

申请号：US12828082

申请日：2010-06-30

申请人： Fritz Redeker ,  John Boyd ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

发明人： Fritz Redeker ,  John Boyd ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

IPC分类号： H01L21/768

CPC分类号： C25D7/123 ,  C23C18/1653 ,  C23C28/023 ,  C23C28/322 ,  C23C28/34 ,  C23C28/341 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.

摘要翻译： 本发明涉及用于半导体器件金属化的方法和系统。 本发明的一个方面是将铜层沉积在阻挡层上以在其间产生基本上无氧的界面的方法。 在一个实施例中，该方法包括提供阻挡层的基本上无氧化物的表面。 该方法还包括在阻挡层的无氧化物表面上沉积一定量的原子层沉积（ALD）铜，以有效地防止阻挡层的氧化。 该方法还包括在ALD铜上沉积间隙填充铜层。 本发明的另一方面是一种用于在阻挡层上沉积铜层以在其间产生基本上无氧的界面的系统。 在一个实施例中，集成系统包括至少一个阻挡层沉积模块。 该系统还包括配置为通过原子层沉积沉积铜的ALD铜沉积模块。 该系统还包括铜间隙填充模块和耦合到至少一个阻挡层沉积模块和ALD铜沉积模块的至少一个传输模块。 转移模块被配置为使得基板可以在基本上不暴露于氧化物形成环境的基础之间传递。

公开(公告)号：US07758404B1

公开(公告)日：2010-07-20

申请号：US11253118

申请日：2005-10-17

申请人： Jason A. Ryder ,  Ji Zhu ,  Mark Wilcoxson ,  Fritz Redeker ,  John P. Parks ,  Charles Ditmore ,  Jeffrey G. Gasparitsch

发明人： Jason A. Ryder ,  Ji Zhu ,  Mark Wilcoxson ,  Fritz Redeker ,  John P. Parks ,  Charles Ditmore ,  Jeffrey G. Gasparitsch

IPC分类号： B24B1/00

CPC分类号： B24B29/04 ,  B24B9/065

摘要： An apparatus, system and method for cleaning a substrate edge include a composite applicator that cleans bevel polymers deposited on wafer edges using frictional contact in the presence of fluids. The composite applicator includes a support material and a plurality of abrasive particles distributed within and throughout the support material. The composite applicator cleans the edge of the wafer by allowing frictional contact of the plurality of abrasive particles with the edge of the wafer in the presence of fluids, such as liquid chemicals, to cut, rip and tear the bevel polymer from the edge of the wafer.

摘要翻译： 用于清洁基材边缘的装置，系统和方法包括复合涂布器，其在存在流体的情况下使用摩擦接触来清洁沉积在晶片边缘上的斜面聚合物。 复合施加器包括支撑材料和分布在支撑材料内部和整个支撑材料上的多个磨料颗粒。 复合涂抹器通过在诸如液体化学品的流体的存在下允许多个研磨颗粒与晶片的边缘摩擦接触来清洁晶片的边缘，以从斜边聚合物的边缘切割，撕裂和撕裂斜面聚合物 晶圆。

公开(公告)号：US07615480B2

公开(公告)日：2009-11-10

申请号：US11820811

申请日：2007-06-20

申请人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

发明人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

IPC分类号： H01L21/20

CPC分类号： H01L23/48 ,  H01L21/4763 ,  H01L21/76898 ,  H01L2924/14

摘要： Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

摘要翻译： 提出了制造三维集成电路的方法，其包括用于三维集成电路的集成的线路通孔的后接触后端。 在一个实施例中，该方法包括通过硬掩模和前金属电介质形成金属插头触点到半导体中的晶体管。 该方法还包括使用图案化的光致抗蚀剂工艺将用于通孔的通孔穿过硬掩模蚀刻到半导体，去除图案化的光致抗蚀剂并使用硬掩模工艺将孔蚀刻到半导体中的量。 所述方法还包括沉积介电衬垫以将所述孔与所述半导体隔离，沉积间隙填充金属以填充所述孔，以及将所述衬底的表面平面化至所述硬掩模。 本发明的另一方面包括根据本发明的方法制造的三维集成电路。

公开(公告)号：US20080315422A1

公开(公告)日：2008-12-25

申请号：US11821051

申请日：2007-06-20

申请人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

发明人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L23/48

CPC分类号： H01L21/44 ,  H01L21/76898 ,  H01L23/48 ,  H01L23/481 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.

摘要翻译： 提供了具有通孔的三维集成电路的制造方法和装置。 本发明的一个方面是用于三维集成电路的通孔通孔的间隙填充方法。 该方法包括提供具有用于通孔通孔的多个孔的半导体晶片，并且沉积保形金属层以部分填充孔以留下开孔。 该方法还包括清除空隙并清洁空隙的表面，并使用干式沉积工艺填充或封闭空隙。 本发明的另一方面是一种用于三维集成电路的电子设备结构。

公开(公告)号：US20080314756A1

公开(公告)日：2008-12-25

申请号：US11820810

申请日：2007-06-20

申请人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

发明人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

IPC分类号： C25D3/38 ,  C25D3/00

CPC分类号： C25D3/00 ,  H01L21/2885 ,  H01L21/32115 ,  H01L21/67005 ,  H01L21/67023 ,  H01L21/67075 ,  H01L21/6708 ,  H01L21/6715 ,  H01L21/768 ,  H01L21/7684 ,  H01L21/76883 ,  H01L21/76898

摘要： Presented are methods and systems for fabricating three-dimensional integrated circuits having large diameter through-hole vias. One embodiment of the present invention provides a method of processing a wafer having holes for through-hole vias. The method comprises plating a gapfill metal on the wafer. The method also comprises chemically or electrochemically deplating a portion of the overburden metal. The method further comprises using chemical mechanical planarization to planarize the gapfill metal and to remove the remaining overburden metal. Another embodiment of the present invention is an integrated system comprising a process chamber for containing the wafer, a plating component integrated with the process chamber, and a deplating component integrated with the process chamber. The plating component is configured to electrochemically plate a gapfill metal onto the wafer to a least partially fill the holes. The deplating component is configured to chemically or to electrochemically remove a portion of the overburden metal formed by the plating component.

摘要翻译： 提出了用于制造具有大直径通孔的三维集成电路的方法和系统。 本发明的一个实施例提供一种处理具有用于通孔过孔的孔的晶片的方法。 该方法包括在晶片上镀覆间隙填充金属。 该方法还包括化学地或电化学地去除一部分覆盖层金属。 该方法还包括使用化学机械平面化来平坦化间隙填充金属并除去剩余的覆盖层金属。 本发明的另一实施例是一种集成系统，其包括用于容纳晶片的处理室，与处理室一体化的电镀部件，以及与处理室一体化的去掉部件。 电镀部件被配置为将间隙填充金属电化学地平板化到晶片上以至少部分地填充孔。 脱镀部件被配置为化学地或电化学地去除由电镀部件形成的覆盖层金属的一部分。

公开(公告)号：US20080142972A1

公开(公告)日：2008-06-19

申请号：US11641361

申请日：2006-12-18

申请人： Fritz Redeker ,  John Boyd ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

发明人： Fritz Redeker ,  John Boyd ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

IPC分类号： H01L21/4763 ,  H01L23/52 ,  C25D3/38

CPC分类号： C25D7/123 ,  C23C18/1653 ,  C23C28/023 ,  C23C28/322 ,  C23C28/34 ,  C23C28/341 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.

摘要翻译： 本发明涉及用于半导体器件金属化的方法和系统。 本发明的一个方面是将铜层沉积在阻挡层上以在其间产生基本上无氧的界面的方法。 在一个实施例中，该方法包括提供阻挡层的基本上无氧化物的表面。 该方法还包括在阻挡层的无氧化物表面上沉积一定量的原子层沉积（ALD）铜，以有效地防止阻挡层的氧化。 该方法还包括在ALD铜上沉积间隙填充铜层。 本发明的另一方面是一种用于在阻挡层上沉积铜层以在其间产生基本上无氧的界面的系统。 在一个实施例中，集成系统包括至少一个阻挡层沉积模块。 该系统还包括配置为通过原子层沉积沉积铜的ALD铜沉积模块。 该系统还包括铜间隙填充模块和耦合到至少一个阻挡层沉积模块和ALD铜沉积模块的至少一个传输模块。 转移模块被配置为使得基板可以在基本上不暴露于氧化物形成环境的基础之间传递。

公开(公告)号：US20080102621A1

公开(公告)日：2008-05-01

申请号：US11591310

申请日：2006-10-31

申请人： Hyungsuk Alexander Yoon ,  Fritz Redeker

发明人： Hyungsuk Alexander Yoon ,  Fritz Redeker

IPC分类号： H01L21/4763

CPC分类号： H01L21/28562 ,  C23C16/029 ,  C23C16/34 ,  C23C16/45529 ,  H01L21/02183 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/3141 ,  H01L21/318 ,  H01L21/76843 ,  H01L21/76846

摘要： Various embodiments provide improved processes and systems that produce a barrier layer with decreasing nitrogen concentration with the increase of film thickness. A barrier layer with decreasing nitrogen concentration with film thickness allows the end of barrier layer with high nitrogen concentration to have good adhesion with a dielectric layer and the end of barrier layer with low nitrogen concentration (or metal-rich) to have good adhesion with copper. An exemplary method of depositing a barrier layer on an interconnect structure is provided. The method includes (a) providing an atomic layer deposition environment, (b) depositing a barrier layer on the interconnect structure with a first nitrogen concentration during a first phase of deposition in the atomic layer deposition environment. The method further includes (c) continuing the deposition of the barrier layer on the interconnect structure with a second nitrogen concentration during a second phase deposition in the atomic layer deposition environment.

摘要翻译： 各种实施方案提供改进的方法和系统，其随着膜厚度的增加产生具有降低的氮浓度的阻挡层。 具有降低氮浓度的膜厚度的阻挡层允许具有高氮浓度的阻挡层的端部与电介质层和低氮浓度（或富含金属）的阻挡层的端部具有良好的粘附性以与铜具有良好的粘合性 。 提供了在互连结构上沉积阻挡层的示例性方法。 该方法包括（a）提供原子层沉积环境，（b）在原子层沉积环境中的第一沉积阶段期间，在互连结构上沉积具有第一氮浓度的势垒层。 该方法还包括（c）在原子层沉积环境中的第二相沉积期间，继续在互连结构上以第二氮浓度沉积阻挡层。

公开(公告)号：US20080057182A1

公开(公告)日：2008-03-06

申请号：US11611758

申请日：2006-12-15

申请人： John Boyd ,  Yezdi Dordi ,  Tiruchirapalli Arunagiri ,  Benjamin Mooring ,  John Parks ,  William Thie ,  Fritz Redeker ,  Arthur Howald ,  Alan Schoepp ,  David Hemker

发明人： John Boyd ,  Yezdi Dordi ,  Tiruchirapalli Arunagiri ,  Benjamin Mooring ,  John Parks ,  William Thie ,  Fritz Redeker ,  Arthur Howald ,  Alan Schoepp ,  David Hemker

IPC分类号： B05D5/12 ,  B05D1/36

CPC分类号： H01L21/67207 ,  H01L21/76843 ,  H01L21/76877

摘要： A method for filling a trench of a substrate in a controlled environment is provided. The method initiates with etching a trench in the substrate in a first chamber of a cluster tool. A barrier layer configured to prevent electromigration is deposited over an exposed surface of the trench in a second chamber of the cluster tool and the trench is filled with a gap fill material deposited directly onto the barrier layer in the cluster tool. A semiconductor device fabricated by the method is also provided.

摘要翻译： 提供了一种用于在受控环境中填充衬底的沟槽的方法。 该方法通过在簇工具的第一室中蚀刻衬底中的沟槽来启动。 构造成防止电迁移的阻挡层沉积在簇工具的第二腔中的沟槽的暴露表面上，并且沟槽填充有直接沉积在簇工具中的阻挡层上的间隙填充材料。 还提供了通过该方法制造的半导体器件。