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115 条记录 (耗时 0.02 秒)

    High performance CMOS transistors using PMD liner stress
    63.
    发明授权
    High performance CMOS transistors using PMD liner stress 有权
    使用PMD衬垫应力的高性能CMOS晶体管

    公开(公告)号：US08809141B2

    公开(公告)日：2014-08-19

    申请号：US11670192

    申请日：2007-02-01

    申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

    发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

    IPC分类号： H01L29/739

    CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7843 ,  Y10S438/954

    摘要： A silicon nitrate layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

    摘要翻译： 在晶体管栅极（40）和源极和漏极区域（70）之上形成硝酸氧化物层（110）。 所形成的氮化硅层（110）包括第一拉伸应力和高氢浓度。 将所形成的氮化硅层（110）进行热退火，将第一拉伸应力转换成大于第一拉伸应力的第二拉伸应力。 在热退火之后，氮化硅层（110）中的氢浓度大于12原子％。

    Antimony ion implantation for semiconductor components
    65.
    发明授权
    Antimony ion implantation for semiconductor components 有权
    半导体元件的锑离子注入

    公开(公告)号：US07795122B2

    公开(公告)日：2010-09-14

    申请号：US11725927

    申请日：2007-03-20

    申请人： Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank S. Ekbote

    发明人： Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank S. Ekbote

    IPC分类号： H01L21/425

    CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/6653 ,  H01L29/7833

    摘要： A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.

    摘要翻译： 公开了一种用于在半导体衬底中注入和活化锑作为掺杂剂的方法。 还公开了一种用于注入和活化锑以形成晶体管的源极/漏极延伸区域的方法，以便实现高激活并避免随后暴露于高温而失活。 该技术有助于形成非常薄的源极/漏极区域，其表现出降低的薄层电阻同时还抑制短沟道效应。 还建议对这些技术的增强用于更精确地注入锑以产生较浅的源极/漏极延伸，并且确保形成源极/漏极延伸区域以使栅极下沉。 还公开了晶体管和其它半导体组件，其包括包含活性锑的掺杂区域，例如根据所公开的方法形成的那些。

    METHOD FOR FORMING A METAL SILICIDE
    67.
    发明申请
    METHOD FOR FORMING A METAL SILICIDE 有权
    形成金属硅化物的方法

    公开(公告)号：US20090004853A1

    公开(公告)日：2009-01-01

    申请号：US11770593

    申请日：2007-06-28

    申请人： Haowen Bu ,  Shashank Ekbote ,  Juanita Deloach

    发明人： Haowen Bu ,  Shashank Ekbote ,  Juanita Deloach

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28518

    摘要： The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing a metal layer on the substrate. The metal layer is annealed within a first temperature range and for a first dwell time of about 10 milliseconds or less to react at least a portion of the metal with the silicon to form a silicide. An unreacted portion of the metal is removed from the substrate. The silicide is annealed within a second temperature range for a second dwell time of about 10 milliseconds or less.

    摘要翻译： 本申请涉及形成金属硅化物层的方法。 该方法包括提供包括硅的衬底并在衬底上沉积金属层。 金属层在第一温度范围内退火，并且在约10毫秒或更短的第一停留时间内使至少一部分金属与硅反应形成硅化物。 将金属的未反应部分从基材上除去。 硅化物在第二温度范围内退火约10毫秒或更短的第二停留时间。

    CMOS transistor using high stress liner layer
    68.
    发明授权
    CMOS transistor using high stress liner layer 有权
    CMOS晶体管采用高应力衬层

    公开(公告)号：US07429517B2

    公开(公告)日：2008-09-30

    申请号：US10845456

    申请日：2004-05-13

    申请人： Zhiqiang Wu ,  Haowen Bu

    发明人： Zhiqiang Wu ,  Haowen Bu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7833 ,  H01L29/6659 ,  H01L29/7843

    摘要： A MOS transistor structure comprising a gate dielectric layer (30), a gate electrode (40), and source and drain regions (70) are formed in a semiconductor substrate (10). First second and third dielectric layers (110), (120), and (130) are formed over the MOS transistor structure. The second and third dielectric structures (120), (130) are removed leaving a MOS transistor with a stressed channel region resulting in improved channel mobility characteristics.

    摘要翻译： 在半导体衬底（10）中形成包括栅极电介质层（30），栅电极（40）以及源极和漏极区（70）的MOS晶体管结构。 在MOS晶体管结构上方形成有第一和第三介质层（110），（120）和（130）。 去除第二和第三介电结构（120）（130），留下具有应力沟道区的MOS晶体管，导致改善的沟道迁移特性。

    Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same
    69.
    发明授权
    Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same 有权
    用于制造具有硅化物栅电极的半导体器件的方法和包括其的集成电路的制造方法

    公开(公告)号：US07338888B2

    公开(公告)日：2008-03-04

    申请号：US10810759

    申请日：2004-03-26

    申请人： Jiong-Ping Lu ,  Haowen Bu ,  Shaofeng Yu ,  Ping Jiang

    发明人： Jiong-Ping Lu ,  Haowen Bu ,  Shaofeng Yu ,  Ping Jiang

    IPC分类号： H01L21/28 ,  H01L21/44 ,  H01L21/76 ,  H01L21/4763

    CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, includes forming a polysilicon gate electrode over a substrate (110) and forming source/drain regions (170) in the substrate (110) proximate the polysilicon gate electrode. The method further includes forming a blocking layer (180) over the source/drain regions (170), the blocking layer (180) comprising a metal silicide, and siliciding the polysilicon gate electrode to form a silicided gate electrode (150).

    摘要翻译： 本发明提供一种制造半导体器件的方法及其制造方法，该集成电路包括该半导体器件。 除了其他可能的步骤之外，用于制造半导体器件（100）的方法包括在衬底（110）上形成多晶硅栅电极，并在靠近多晶硅栅电极的衬底（110）中形成源/漏区（170）。 该方法还包括在源极/漏极区域（170）上形成阻挡层（180），阻挡层（180）包括金属硅化物，并硅化多晶硅栅电极以形成硅化物栅电极（150）。

    A METHOD OF MANUFACTURING GATE SIDEWALLS THAT AVOIDS RECESSING
    70.
    发明申请
    A METHOD OF MANUFACTURING GATE SIDEWALLS THAT AVOIDS RECESSING 有权
    制造门禁的门控方法

    公开(公告)号：US20070287258A1

    公开(公告)日：2007-12-13

    申请号：US11422952

    申请日：2006-06-08

    申请人： Jong Shik Yoon ,  Amitava Chatterjee ,  Haowen Bu

    发明人： Jong Shik Yoon ,  Amitava Chatterjee ,  Haowen Bu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6656 ,  H01L21/2652 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659

    摘要： A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spacers of a gate structure located adjacent to the source and drain regions. The method further comprises depositing a second oxide layer selectively on the exposed source and drain regions and then removing lateral segments of the silicon nitride sidewall spacers.

    摘要翻译： 一种制造半导体器件的方法，包括去除沉积在半导体衬底上的第一氧化物层，从而暴露衬底的源极和漏极区域。 第一氧化物层被配置为用于形成邻近源极和漏极区的栅极结构的氮化硅侧壁间隔物的蚀刻停止。 该方法还包括在暴露的源极和漏极区上选择性地沉积第二氧化物层，然后去除氮化硅侧壁间隔物的侧向部分。