公开(公告)号：US20070102705A1

公开(公告)日：2007-05-10

申请号：US11644863

申请日：2006-12-21

申请人： Gurtej Sandhu ,  Shubneesh Batra ,  Pierre Fazan

发明人： Gurtej Sandhu ,  Shubneesh Batra ,  Pierre Fazan

IPC分类号： H01L29/04 ,  H01L29/786

CPC分类号： H01L29/78678 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/04 ,  H01L29/6675 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78672 ,  H01L29/78675

摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.

摘要翻译： 相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。 薄膜晶体管可以被制造为底部门控或顶部门控。 可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。 优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中并且在晶界内引入氟以使所述晶界钝化，但是足够低以防止含氟层与 多晶薄膜层。

公开(公告)号：US20070048630A1

公开(公告)日：2007-03-01

申请号：US11472598

申请日：2006-06-21

申请人： Gurtej Sandhu

发明人： Gurtej Sandhu

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： H01L28/91 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/31144 ,  H01L27/10852

摘要： The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which capacitor container openings are incorporated into DRAM arrays. An exemplary method of forming a reticle includes formation of a radiation-imageable layer over a material. A lattice pattern is then formed within the radiation-imageable layer, with the lattice pattern defining a plurality of islands of the radiation-imageable layer. The lattice-patterned radiation-imageable layer is utilized as a mask while subjecting the material under the lattice-patterned layer to an etch which transfers the lattice pattern into the material. The etch forms a plurality of pillars which extend only partially into the material, with the pillars being spaced from one another by gaps. The gaps are subsequently narrowed with a second material which only partially fills the gaps.

摘要翻译： 本发明包括形成用于压印光刻的掩模版的方法，形成电容器容器开口的方法，以及将电容器容器开口并入到DRAM阵列中的方法。 形成掩模版的示例性方法包括在材料上形成可辐射成像层。 然后在可辐射成像层内形成格子图案，其中格子图案限定可辐射成像层的多个岛。 将格子图案的可辐射成像层用作掩模，同时使晶格图案层下的材料经历将晶格图案转移到材料中的蚀刻。 蚀刻形成多个柱，其仅部分地延伸到材料中，柱通过间隙彼此间隔开。 间隙随后仅用部分填充间隙的第二材料变窄。

公开(公告)号：US20070045119A1

公开(公告)日：2007-03-01

申请号：US11217170

申请日：2005-09-01

申请人： Gurtej Sandhu

发明人： Gurtej Sandhu

IPC分类号： C25D9/04

CPC分类号： C25D15/00 ,  B82Y30/00 ,  B82Y99/00 ,  C25D13/02

摘要： Methods and apparatus for forming devices using nanotubes. In one embodiment, an apparatus for depositing nanotubes onto a workpiece comprises a vessel configured to contain a deposition fluid having a plurality of nanotubes including first nanotubes having a first characteristic and second nanotubes having a second characteristic. The apparatus further includes a sorting unit in the vessel configured to selectively isolate or otherwise sort the first nanotubes from the second nanotubes, and a field unit in the vessel configured to attach the first nanotubes to the workpiece. For example, the field unit can attach the first nanotubes to the workpiece such that the first nanotubes are at least generally parallel to each other and in a desired orientation relative to the workpiece.

摘要翻译： 使用纳米管形成器件的方法和装置。 在一个实施例中，用于将纳米管沉积到工件上的装置包括：容器，其构造成容纳具有多个纳米管的沉积流体，所述多个纳米管包括具有第一特征的第一纳米管和具有第二特征的第二纳米管。 该装置还包括在容器中的分选单元，其被配置为选择性地将第一纳米管与第二纳米管分离或以其他方式分类，并且容器中的场单元被配置为将第一纳米管附接到工件。 例如，场单元可以将第一纳米管附接到工件，使得第一纳米管至少大体上彼此平行并且相对于工件以期望的取向。

公开(公告)号：US20070020870A1

公开(公告)日：2007-01-25

申请号：US11495655

申请日：2006-07-28

申请人： Gurtej Sandhu

发明人： Gurtej Sandhu

IPC分类号： H01L21/20

CPC分类号： H01L27/10852 ,  H01L21/28518 ,  H01L21/28568 ,  H01L27/10817 ,  H01L27/1085 ,  H01L28/84 ,  H01L28/90

摘要： A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride material overlying the conductive hemispherical grained material and the metal silicide material. The semiconductor capacitor structure is fabricated by forming a base of metal silicide material along the sidewalls of an insulative material having an opening therein, forming sidewalls of conductive hemispherical grained material on the metal silicide material, and forming a metal nitride material overlying the conductive hemispherical grained material and the metal silicide material.

摘要翻译： 一种半导体电容器结构，包括导电半球形颗粒材料的侧壁，金属硅化物材料的基底和覆盖在导电半球形颗粒材料和金属硅化物材料上的金属氮化物材料。 半导体电容器结构通过沿着其中具有开口的绝缘材料的侧壁形成金属硅化物材料的基底来制造，在金属硅化物材料上形成导电半球状晶粒材料的侧壁，并且形成覆盖导电半球形晶粒的金属氮化物材料 材料和金属硅化物材料。

公开(公告)号：US20060263997A1

公开(公告)日：2006-11-23

申请号：US11495435

申请日：2006-07-28

申请人： Gurtej Sandhu

发明人： Gurtej Sandhu

IPC分类号： H01L21/44 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L21/28518 ,  H01L21/28568 ,  H01L27/10817 ,  H01L27/1085 ,  H01L28/84 ,  H01L28/90

摘要： A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride material overlying the conductive hemispherical grained material and the metal silicide material. The semiconductor capacitor structure is fabricated by forming a base of metal silicide material along the sidewalls of an insulative material having an opening therein, forming sidewalls of conductive hemispherical grained material on the metal silicide material, and forming a metal nitride material overlying the conductive hemispherical grained material and the metal silicide material.

公开(公告)号：US20060263947A1

公开(公告)日：2006-11-23

申请号：US11496315

申请日：2006-07-31

申请人： Mark Fischer ,  Zhiping Yin ,  Thomas Glass ,  Kunal Parekh ,  Gurtej Sandhu

发明人： Mark Fischer ,  Zhiping Yin ,  Thomas Glass ,  Kunal Parekh ,  Gurtej Sandhu

IPC分类号： H01L21/82

CPC分类号： H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. The fuse also includes an outer insulating element that overlays and encloses the heat conductive element and the absorption element.

公开(公告)号：US20060258131A1

公开(公告)日：2006-11-16

申请号：US11418582

申请日：2006-05-04

申请人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Cem Basceri ,  Eric Blomiley

发明人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Cem Basceri ,  Eric Blomiley

IPC分类号： H01L21/44

CPC分类号： H01L29/66787 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66742 ,  H01L29/78642

摘要： This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.

公开(公告)号：US20060258113A1

公开(公告)日：2006-11-16

申请号：US11460021

申请日：2006-07-26

申请人： Gurtej Sandhu ,  Guy Blalock

发明人： Gurtej Sandhu ,  Guy Blalock

IPC分类号： H01L29/94 ,  H01L21/20

CPC分类号： H01L27/10852 ,  H01L21/02183 ,  H01L21/02197 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31637 ,  H01L21/31654 ,  H01L27/10811 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/56 ,  H01L28/65 ,  H01L28/91

摘要： A capacitor structure and method of forming it are described. In particular, a high-K dielectric oxide is provided as the capacitor dielectric. The high-K dielectric is deposited in a series of thin layers and oxidized in a series of oxidation steps, as opposed to a depositing a single thick layer. Further, at least one of the oxidation steps is less aggressive than the oxidation environment or environments that would be used to deposit the single thick layer. This allows greater control over oxidizing the dielectric and other components beyond the dielectric.

摘要翻译： 描述电容器结构及其形成方法。 特别地，提供高K电介质氧化物作为电容器电介质。 与沉积单个厚层相反，高K电介质沉积在一系列薄层中并在一系列氧化步骤中被氧化。 此外，至少一个氧化步骤比用于沉积单个厚层的氧化环境或环境更不具有侵蚀性。 这允许更好地控制电介质和超过电介质的其它组件的氧化。

公开(公告)号：US20060258086A1

公开(公告)日：2006-11-16

申请号：US11486512

申请日：2006-07-13

申请人： H. Manning ,  Kunal Parekh ,  Cem Basceri ,  Gurtej Sandhu

发明人： H. Manning ,  Kunal Parekh ,  Cem Basceri ,  Gurtej Sandhu

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/66787 ,  H01L27/10808 ,  H01L27/10876

摘要： The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.

公开(公告)号：US20060257570A1

公开(公告)日：2006-11-16

申请号：US11490622

申请日：2006-07-21

申请人： Garo Derderian ,  Gurtej Sandhu

发明人： Garo Derderian ,  Gurtej Sandhu

IPC分类号： C23C16/00

CPC分类号： C23C16/45525 ,  B05D1/185 ,  C23C16/04 ,  C23C16/045 ,  C23C16/403 ,  C23C16/45531 ,  C30B25/18 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/3162

摘要： A deposition method includes contacting a substrate with a first initiation precursor and forming a first portion of an initiation layer on the substrate. At least a part of the substrate is contacted with a second initiation precursor different from the first initiation precursor and a second portion of the initiation layer is formed on the substrate. The substrate may be simultaneously contacted with a plurality of initiation precursors, forming on the substrate and initiation layer comprising components, derived from each of the plurality of initiation precursors. An initiation layer may be contacted with a deposition precursor, forming a deposition layer on the initiation layer. The deposition layer may be contacted with a second initiation precursor different from the first initiation precursor forming a second initiation layer over the substrate. Also, a first initiation layer may be formed substantially selectively on a first-type substrate surface relative to a second-type substrate surface and contacted with a deposition precursor, forming a deposition layer substantially selectively over the first-type substrate surface.

摘要翻译： 沉积方法包括使基底与第一起始前体接触，并在基底上形成起始层的第一部分。 基板的至少一部分与不同于第一起始前体的第二起始前体接触，并且在基板上形成起始层的第二部分。 衬底可以与多个起始前体同时接触，在衬底上形成并且起始层包含衍生自多个引发前体中的每一个的组分。 引发层可以与沉积前体接触，在引发层上形成沉积层。 沉积层可以与不同于第一起始前体的第二引发前体接触，从而在衬底上形成第二起始层。 此外，第一起始层可以基本上选择性地形成在相对于第二类型衬底表面的第一类型衬底表面上，并与沉积前体接触，在第一类型衬底表面上基本上选择性地形成沉积层。