公开(公告)号：US6163225A

公开(公告)日：2000-12-19

申请号：US305976

申请日：1999-05-05

Applicant: Rajesh Sundaram ,  Sandeep K. Guliani

Inventor： Rajesh Sundaram ,  Sandeep K. Guliani

IPC: H03B5/04 ,  H03B5/24

CPC classification number: H03B5/04 ,  H03B5/24

Abstract: A method for generating a positive temperature correlated clock frequency is described. The method comprises conducting current through a resistor to charge a capacitor. When the capacitor is charged to a trip point of the inverter at the input of the inverter chain, a transition in an output signal of an inverter chain is triggered. The capacitor is discharged through a grounding device when the output signal activates said grounding device.

Abstract translation: 描述了用于产生正温度相关时钟频率的方法。 该方法包括通过电阻器传导电流以对电容器充电。 当电抗器在变频器链的输入端被充电到变频器的跳变点时，触发逆变器链输出信号的转变。 当输出信号激活所述接地装置时，电容器通过接地装置放电。

公开(公告)号：US09354989B1

公开(公告)日：2016-05-31

申请号：US13251916

申请日：2011-10-03

Applicant: Priya Sehgal ,  Kaladhar Voruganti ,  Rajesh Sundaram

Inventor： Priya Sehgal ,  Kaladhar Voruganti ,  Rajesh Sundaram

IPC: G06F12/08 ,  G06F12/00 ,  G06F11/14

CPC classification number: G06F11/1482 ,  G06F11/00

Abstract: Region based admission and eviction control can be used for managing resources (e.g., caching resources) shared by competing workloads with different SLOs in hybrid aggregates. A “region” or “phase” refers to different incoming loads of a workload (e.g., different working set sizes, different intensities of the workload, etc.). These regions can be identified and then utilized along with other factors (e.g., incoming loads of other workloads, maximum cache allocation size, service level objectives, and others factors/parameters) in managing cache storage resources.

Abstract translation: 基于区域的准入和撤离控制可用于管理与混合聚合中的不同SLO的竞争工作负载共享的资源（例如，缓存资源）。 “区域”或“相位”是指工作负载的不同输入负载（例如，不同的工作集大小，工作负载的不同强度等）。 这些区域可以在管理高速缓存存储资源中被识别并随后与其他因素（例如，其他工作负载的进入负载，最大缓存分配大小，服务水平目标和其他因素/参数）一起使用。

公开(公告)号：US09195589B2

公开(公告)日：2015-11-24

申请号：US13977084

申请日：2011-12-27

Applicant: Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Blaise Fanning

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Blaise Fanning

IPC: G06F3/00 ,  G06F12/02 ,  G06F9/30 ,  G06F1/32 ,  G11C16/06

CPC classification number: G11C13/0038 ,  G06F1/3275 ,  G06F9/30101 ,  G06F12/0246 ,  G11C13/0004 ,  G11C13/0033 ,  G11C16/06 ,  Y02D10/14

Abstract: Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.

Abstract translation: 公开了用于非易失性存储器的自适应配置的示例。 示例包括配置为包括默认值和更新值以指示非易失性存储器的一个或多个配置的模式寄存器。 这些示例还可以包括可以指示存储器地址长度和/或操作功率状态的配置表中维护的可发现功能。

公开(公告)号：US20150269100A1

公开(公告)日：2015-09-24

申请号：US14731183

申请日：2015-06-04

Applicant: Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

IPC: G06F13/28 ,  G06F12/02 ,  G06F13/42 ,  G11C7/22 ,  G06F1/12 ,  G06F13/16

CPC classification number: G06F13/28 ,  G06F1/12 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/385 ,  G06F13/409 ,  G06F13/42 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C7/222 ,  H04L5/00 ,  H04L7/00 ,  Y02D10/14 ,  Y02D10/151

Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

Abstract translation: 通过存储器总线访问非易失性存储器或存储器件。 存储器总线具有通常用于易失性存储器件的电接口。 耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。 控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。 控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。 存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。

公开(公告)号：US09043530B1

公开(公告)日：2015-05-26

申请号：US13442194

申请日：2012-04-09

Applicant: Rajesh Sundaram ,  Douglas Paul Doucette ,  David Grunwald ,  Jeffrey S. Kimmel ,  Ashish Prakash

Inventor： Rajesh Sundaram ,  Douglas Paul Doucette ,  David Grunwald ,  Jeffrey S. Kimmel ,  Ashish Prakash

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/08

CPC classification number: G06F12/0866 ,  G06F3/0611 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/068 ,  G06F3/0685 ,  G06F12/0802 ,  G06F2003/0691 ,  G06F2003/0692 ,  G06F2212/1024 ,  G06F2212/217 ,  G06F2212/222 ,  G06F2212/281

Abstract: Among other things, one or more techniques and/or systems are provided for storing data within a hybrid storage aggregate comprising a lower-latency storage tier and a higher-latency storage tier. In particular, frequently accessed data, randomly accessed data, and/or short lived data may be stored (e.g., read caching and/or write caching) within the lower-latency storage tier. Infrequently accessed data and/or sequentially accessed data may be stored within the higher-latency storage tier. Because the hybrid storage aggregate may comprise a single logical container derived from the higher-latency storage tier and the lower-latency storage tier, additional storage and/or file system functionality may be implemented across the storage tiers. For example, deduplication functionality, caching functionality, backup/restore functionality, and/or other functionality may be provided through a single file system (or other type of arrangement) and/or a cache map implemented within the hybrid storage aggregate.

Abstract translation: 除其他之外，提供一个或多个技术和/或系统用于在包括较低延迟存储层和较高延迟存储层的混合存储聚合中存储数据。 特别地，经常访问的数据，随机访问的数据和/或短寿命数据可以在较低延迟存储层内被存储（例如，读取高速缓存和/或写入高速缓存）。 不经常访问的数据和/或顺序访问的数据可以存储在更高延迟的存储层中。 因为混合存储聚合可以包括从较高延迟存储层和较低延迟存储层导出的单个逻辑容器，所以可以跨存储层实现附加的存储和/或文件系统功能。 例如，重复数据删除功能，缓存功能，备份/恢复功能和/或其他功能可以通过单个文件系统（或其他类型的安排）和/或在混合存储聚合中实现的缓存映射来提供。

公开(公告)号：US20140258804A1

公开(公告)日：2014-09-11

申请号：US13792597

申请日：2013-03-11

Applicant: Kiran Pangal ,  Prashant S. Damle ,  Rajesh Sundaram ,  Shekoufeh Qawami ,  Julie M. Walker ,  Doyle Rivers

Inventor： Kiran Pangal ,  Prashant S. Damle ,  Rajesh Sundaram ,  Shekoufeh Qawami ,  Julie M. Walker ,  Doyle Rivers

IPC: H03M13/05

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  H03M13/05 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/27 ,  H03M13/6508

Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

Abstract translation: 可以通过确定一组存储器阵列的逻辑阵列地址并且至少部分地基于该组内的至少两个存储器阵列的逻辑位置将逻辑阵列地址变换为至少两个唯一阵列地址来减少不可校正的存储器错误 的存储器阵列。 然后使用至少两个唯一的阵列地址分别访问至少两个存储器阵列。

公开(公告)号：US08607089B2

公开(公告)日：2013-12-10

申请号：US13111839

申请日：2011-05-19

Applicant: Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

IPC: G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00

CPC classification number: G06F13/28 ,  G06F1/12 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/385 ,  G06F13/409 ,  G06F13/42 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C7/222 ,  H04L5/00 ,  H04L7/00 ,  Y02D10/14 ,  Y02D10/151

Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

公开(公告)号：US20130238851A1

公开(公告)日：2013-09-12

申请号：US13413877

申请日：2012-03-07

Applicant: Koling Chang ,  Rajesh Sundaram ,  Douglas P. Doucette ,  Ravikanth Dronamraju

Inventor： Koling Chang ,  Rajesh Sundaram ,  Douglas P. Doucette ,  Ravikanth Dronamraju

IPC: G06F12/08

CPC classification number: G06F12/0871 ,  G06F3/061 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0685 ,  G06F12/0895

Abstract: Methods and apparatuses for operating a hybrid storage aggregate are provided. In one example, such a method includes operating a first tier of physical storage of the hybrid storage aggregate as a cache for a second tier of physical storage of the hybrid storage aggregate. The first tier of physical storage includes a plurality of assigned blocks. The method also includes updating metadata of the assigned blocks in response to an event associated with at least one of the assigned blocks. The metadata includes block usage information tracking more than two possible usage states per assigned block. The method can further include processing the metadata to determine a caching characteristic of the assigned blocks.

Abstract translation: 提供了用于操作混合存储集合体的方法和装置。 在一个示例中，这种方法包括操作混合存储聚合体的第一层物理存储作为混合存储聚合体的第二物理存储层的缓存。 第一层物理存储包括多个分配块。 该方法还包括响应于与所分配的块中的至少一个相关联的事件来更新所分配的块的元数据。 元数据包括跟踪每个分配块的两个以上可能使用状态的块使用信息。 该方法还可以包括处理元数据以确定所分配块的高速缓存特性。

公开(公告)号：US08364847B2

公开(公告)日：2013-01-29

申请号：US12050027

申请日：2008-03-17

Applicant: Dmitry Anipko ,  David G. Thaler ,  Deepak Bansal ,  Benjamin M. Schultz ,  Rajesh Sundaram

Inventor： Dmitry Anipko ,  David G. Thaler ,  Deepak Bansal ,  Benjamin M. Schultz ,  Rajesh Sundaram

IPC: G06F15/16

CPC classification number: H04L61/2007 ,  H04L29/12264 ,  H04L29/1232 ,  H04L29/1249 ,  H04L61/2046 ,  H04L61/2092 ,  H04L61/256

Abstract: Disclosed are an approach form managing and assigning addresses in a connectivity platform that allows for proprietary connectivity modules (Providers) to plug into the operating system. In this disclosure, when a user/application/computing device, connects to another user on another computing device an address is generated for that user. However, because of a limited number of addresses that are available in an address space, it is necessary to ensure that a conflicting address is not present. To ensure this the connectivity platform determines if the address assigned is in conflict with another address associated with users that are located on the other computing devices. If an address is found to be in conflict the connectivity platform reassigns the address until a non-conflicting address is found. If a non-conflicting address cannot be found the connectivity platform blocks the connection between the user and the other user.

Abstract translation: 公开了一种在连接平台中管理和分配地址的方法，允许专有连接模块（供应商）插入操作系统。 在本公开中，当用户/应用/计算设备连接到另一计算设备上的另一用户时，为该用户生成地址。 但是，由于地址空间中可用的地址数量有限，因此必须确保不存在冲突的地址。 为了确保这一点，连接平台确定分配的地址是否与位于其他计算设备上的用户相关联的另一个地址冲突。 如果发现地址处于冲突状态，连接平台会重新分配地址，直到找到不冲突的地址。 如果无法找到不冲突的地址，则连接平台将阻止用户与其他用户之间的连接。

公开(公告)号：US20120297231A1

公开(公告)日：2012-11-22

申请号：US13111839

申请日：2011-05-19

Applicant: Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

IPC: G06F1/12

CPC classification number: G06F13/28 ,  G06F1/12 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/385 ,  G06F13/409 ,  G06F13/42 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C7/222 ,  H04L5/00 ,  H04L7/00 ,  Y02D10/14 ,  Y02D10/151

Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

Abstract translation: 通过存储器总线访问非易失性存储器或存储器件。 存储器总线具有通常用于易失性存储器件的电接口。 耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。 控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。 控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。 存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。