公开(公告)号：US20250048724A1

公开(公告)日：2025-02-06

申请号：US18921317

申请日：2024-10-21

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Brian Edward Hornung

IPC: H01L27/088 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.

公开(公告)号：US11869956B2

公开(公告)日：2024-01-09

申请号：US17490558

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar

IPC: H01L21/266 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66537 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/66492 ,  H01L29/7838

Abstract: A channel stop and well dopant migration control implant (e.g., of argon) can be used in the fabrication of a transistor (e.g., PMOS), either around the time of threshold voltage adjust and well implants prior to gate formation, or as a through-gate implant around the time of source/drain extension implants. With its implant depth targeted about at or less than the peak of the concentration of the dopant used for well and channel stop implants (e.g., phosphorus) and away from the substrate surface, the migration control implant suppresses the diffusion of the well and channel stop dopant to the surface region, a more retrograde concentration profile is achieved, and inter-transistor threshold voltage mismatch is improved without other side effects. A compensating through-gate threshold voltage adjust implant (e.g., of arsenic) or a threshold voltage adjust implant of increased dose can increase the magnitude of the threshold voltage to a desired level.

公开(公告)号：US20230154971A1

公开(公告)日：2023-05-18

申请号：US18093951

申请日：2023-01-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar

IPC: H01L27/07 ,  H01L21/8238

CPC classification number: H01L28/20 ,  H01L27/0738 ,  H01L21/823857

Abstract: Methods and semiconductor circuits are described in which a polysilicon resistor body is formed over a semiconductor substrate. A first dopant species is implanted into the polysilicon resistor body at a first angle about parallel to a surface normal of a topmost surface of the polysilicon resistor body. A second dopant species is implanted into the polysilicon resistor body at a second angle greater than about 10° relative to the surface normal. The combination of implants reduces the different between the temperature coefficient (tempco) of resistance of narrow resistors relative to the tempco of wide resistors, and brings the tempco of the resistors closer to a preferred value of zero.

公开(公告)号：US20220102553A1

公开(公告)日：2022-03-31

申请号：US17548827

申请日：2021-12-13

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Wayne Bather ,  Narendra Singh Mehta

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66

Abstract: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.

公开(公告)号：US11205578B2

公开(公告)日：2021-12-21

申请号：US16161920

申请日：2018-10-16

Applicant: Texas Instruments Incorporated

Inventor： Brian K. Kirkpatrick ,  Kenneth Palomino ,  Mahalingam Nandakumar

IPC: H01L21/324 ,  H01L49/02 ,  H01L27/07 ,  H01L21/225 ,  H01L21/268 ,  H01L27/06 ,  H01L21/265

Abstract: A method of fabricating an integrated circuit (IC) includes providing a substrate having a semiconductor surface layer thereon including a field dielectric in a portion of the semiconductor surface layer and a pair of matched devices in at least one of a CMOS area, BiCMOS area, bipolar transistor area, and a resistor area. Dopants are ion implanted into the at least one of the CMOS area, the BiCMOS area, the bipolar transistor area, and the resistor area. The substrate is annealed in a processing chamber of a rapid thermal processor (RTP). The annealing comprises an initial temperature stabilization step including first annealing at a lower temperature for a first time of at least 20 seconds, and then a second annealing comprising ramping from the lower temperature to a peak higher temperature that is at least 100° C. higher (>) than the lower temperature.

公开(公告)号：US11011508B2

公开(公告)日：2021-05-18

申请号：US16220881

申请日：2018-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar ,  Robert Callaghan Taft ,  Alan Erik Segervall ,  Muhammad Yusuf Ali

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/06 ,  H01L27/08 ,  H01L27/092 ,  H01L29/66

Abstract: An electronic device, e.g. an integrated circuit, is formed on a P-type lightly-doped semiconductor substrate having an N-type buried layer. First and second N-wells extend from a surface of the substrate to the buried layer. A first NSD region is located within the first N-well, and a second NSD region is located within the second N-well. A PSD region extends from the substrate surface into the substrate and is located between the first and second NSD regions. A P-type lightly-doped portion of the substrate is located between the N-well and the substrate surface and between the PSD region and the first and second NSD regions.

公开(公告)号：US20210125872A1

公开(公告)日：2021-04-29

申请号：US16662967

申请日：2019-10-24

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L21/822 ,  H01L27/01 ,  H01L21/265 ,  H01L21/266

Abstract: Fabrication of an integrated circuit includes forming a photoresist layer over a substrate. Target regions defined on the substrate are exposed using a reticle that defines a first exposure window for a first doped structure of a first type; the first exposure window has a first plurality of openings and a first plurality of dopant blocking regions. A respective exposure dose for each of the target regions is determined by an exposure map and provides controlled variations in the size of the first plurality of openings across the plurality of target regions. Subsequent to the exposure and to developing the photoresist, a dopant is implanted into the substrate through the first plurality of openings.

公开(公告)号：US20210089694A1

公开(公告)日：2021-03-25

申请号：US16944890

申请日：2020-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar ,  Murlidhar Bashyam ,  Alwin Tsao ,  Douglas Newman

IPC: G06F30/367 ,  H01L21/66 ,  G06F30/398 ,  G06F30/392 ,  G06F30/373 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

Abstract: The present disclosure provides a method for adjusting implant parameter conditions in semiconductor processing by wafer and by wafer zone using in-line measurements from previous operations and a feed-forward computer model. The feed-forward model is based on a sensitivity map of in-line measured data and its effect of electrical performance. Feed-forward computer models that adjust implant parameters by wafer and by zone improve both wafer-to-wafer and within wafer electrical uniformity in semiconductor devices.

公开(公告)号：US10249621B2

公开(公告)日：2019-04-02

申请号：US15380546

申请日：2016-12-15

Applicant: Texas Instruments Incorporated

Inventor： Mark Robert Visokay ,  Tae S. Kim ,  Mahalingam Nandakumar ,  Eric D. Rullan ,  Gregory B. Shinn

IPC: H01L27/00 ,  H01L27/088 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L23/522 ,  H01L29/49

Abstract: A method of limiting plasma charging damage on ICs. A die includes gate stacks on active areas defined by a field dielectric. A pre-metal dielectric (PMD) layer is over the gate electrode. A contact masking material pattern is defined on the PMD layer including first contact defining features for forming active contacts and second contact defining features for forming dummy contacts (DC's) including over active areas and gate electrodes. Contacts are etched through the PMD layer using the contact masking material pattern to form active contacts and DC's. A patterned metal 1 (M1) layer is formed including first M1 portions over the active contacts and dummy M1 portions over the DC's. Metallization processing follows including forming interconnects so that the active contacts are connected to MOS transistors on the IC, and the DC's are not electrically connected to the MOS transistors.

公开(公告)号：US09960162B2

公开(公告)日：2018-05-01

申请号：US15184405

申请日：2016-06-16

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Mahalingam Nandakumar

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.