公开(公告)号：US11211471B1

公开(公告)日：2021-12-28

申请号：US17017666

申请日：2020-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yong-Yi Lin ,  Yang-Ju Lu ,  Yu-Lung Shih ,  Ji-Min Lin ,  Ching-Yang Chuang ,  Kun-Ju Li

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/40

Abstract: The present invention discloses a metal gate process. A sacrificial nitride layer is introduced during the fabrication of metal gates. The gate height can be well controlled by introducing the sacrificial nitride layer. Further, the particle fall-on problem can be effectively solved.

公开(公告)号：US11145602B2

公开(公告)日：2021-10-12

申请号：US16786919

申请日：2020-02-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Jhih-Yuan Chen ,  Hsin-Jung Liu ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Fu-Chun Hsiao ,  Ji-Min Lin ,  Chun-Han Chen

IPC: H01L23/544 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer independently includes silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.

公开(公告)号：US11004897B2

公开(公告)日：2021-05-11

申请号：US16531108

申请日：2019-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC: H01L29/82 ,  H01L27/22 ,  H01L43/12 ,  H01F41/34 ,  G11C11/16 ,  H01F10/32 ,  H01L43/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.

公开(公告)号：US10446745B1

公开(公告)日：2019-10-15

申请号：US16004446

申请日：2018-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Kun-Ju Li

IPC: H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L27/12

Abstract: A method of manufacturing a magnetoresistive random access memory cell includes the following steps. A first dielectric layer including a first metal line therein is formed on a substrate. A patterned second dielectric layer is formed over the first dielectric layer, wherein the patterned second dielectric layer includes a recess exposing the first metal line. A barrier layer conformally covers the recess and the patterned second dielectric layer. A metal fills up the recess and on the barrier layer. The metal is planarized until the barrier layer being exposed by serving the barrier layer as a stop layer. A magnetic tunneling junction and a top electrode over the metal are formed, thereby a magnetoresistive random access memory cell being formed.

公开(公告)号：US20180061656A1

公开(公告)日：2018-03-01

申请号：US15245194

申请日：2016-08-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC: H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/31055 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02227 ,  H01L21/02271 ,  H01L21/31111 ,  H01L21/823431

Abstract: A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a SiO layer. And the SiO layer is formed the on the SiN layer. Subsequently, a planarization process is performed to remove a portion of the SiO layer to expose the SiN layer.

公开(公告)号：US09875909B1

公开(公告)日：2018-01-23

申请号：US15220365

申请日：2016-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC: H01L21/321 ,  H01L21/308 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/302 ,  H01L21/306

CPC classification number: H01L21/3081 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0273 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31056 ,  H01L21/31058 ,  H01L21/3212

Abstract: A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.

公开(公告)号：US20170047251A1

公开(公告)日：2017-02-16

申请号：US14824091

申请日：2015-08-12

Applicant: United Microelectronics Corp.

Inventor： Yi-Hui Lee ,  Kun-Ju Li ,  Wei-Cyuan Lo ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/768 ,  H01L21/311 ,  H01L29/78 ,  H01L21/3105

CPC classification number: H01L21/76895 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device includes: providing a semiconductor having active regions; depositing a dielectric layer on the semiconductor; forming a patterned etch mask on the dielectric layer; depositing a further dielectric layer on the dielectric layer and the patterned etch mask; planarizing the further dielectric layer until the patterned etch mask is exposed; and forming a further patterned etch mask having an opening on the further dielectric layer so that portions of the patterned etch mask are exposed from the opening.

Abstract translation: 一种制造半导体器件的方法包括：提供具有有源区的半导体; 在半导体上沉积介电层; 在介电层上形成图案化的蚀刻掩模; 在介电层和图案化的蚀刻掩模上沉积另外的介电层; 平面化另外的介电层，直到图案化的蚀刻掩模曝光; 以及形成另一图案化的蚀刻掩模，其在所述另外的电介质层上具有开口，使得所述图案化蚀刻掩模的部分从所述开口露出。

公开(公告)号：US20170040435A1

公开(公告)日：2017-02-09

申请号：US14840041

申请日：2015-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Tsen Lu ,  Chien-Ming Lai ,  Lu-Sheng Chou ,  Ya-Huei Tsai ,  Ching-Hsiang Chiu ,  Yu-Tung Hsiao ,  Chen-Ming Huang ,  Kun-Ju Li ,  Yu-Ping Wang

IPC: H01L29/66 ,  H01L29/49 ,  C22C32/00 ,  H01L29/423

CPC classification number: H01L29/66545 ,  B32B1/00 ,  B32B18/00 ,  C22C32/0068 ,  H01L21/28088 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/511

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.

Abstract translation: 公开了一种半导体器件。 半导体器件包括衬底和衬底上的栅极结构。 栅极结构包括在衬底上的高k电介质层和高k电介质层上的底部阻挡金属（BBM）层。 优选地，BBM层包括顶部，中间部分和底部，其中顶部是富氮部分，中部和底部是富钛部分。

公开(公告)号：US09466484B1

公开(公告)日：2016-10-11

申请号：US14859491

申请日：2015-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Yu-Ting Li ,  Po-Cheng Huang ,  Fu-Shou Tsai ,  Wu-Sian Sie ,  I-Lun Hung ,  Chun-Tsen Lu ,  Shih-Ming Lin ,  Lan-Ping Chang

IPC: H01L21/31 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11

CPC classification number: H01L27/11 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/1116

Abstract: A manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A plurality of fin structures are formed in a first area and a second area of a substrate. A first density of the fin structures in the first area is lower than a second density of the fin structures in the second area. A gate dielectric layer is formed on the fin structures. An amorphous silicon layer is formed on the gate dielectric layer and the fin structures in the first area and the second area. Part of the amorphous silicon layer which is disposed in the first area is annealed to form a crystalline silicon layer by a laser. The crystalline silicon layer disposed in the first area and the amorphous silicon layer disposed in the second area are polished.

Abstract translation: 提供一种半导体器件的制造方法。 该制造方法包括以下步骤。 在基板的第一区域和第二区域中形成多个翅片结构。 第一区域中的翅片结构的第一密度低于第二区域中的翅片结构的第二密度。 栅极电介质层形成在鳍结构上。 在第一区域和第二区域中的栅介质层和鳍结构上形成非晶硅层。 设置在第一区域中的非晶硅层的一部分被退火以通过激光形成晶体硅层。 设置在第一区域中的结晶硅层和设置在第二区域中的非晶硅层被抛光。

公开(公告)号：US09384996B2

公开(公告)日：2016-07-05

申请号：US14272672

申请日：2014-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Kun-Ju Li ,  Chang-Hung Kung ,  Yue-Han Wu ,  Chih-Chien Liu

IPC: H01L21/3105 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/3105 ,  H01L21/31055 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating depositions are substantially aligned with the top surface of the insulation.

Abstract translation: 提供一种制造半导体器件的方法及其制造方法。 根据实施例，提供具有至少具有多个第一栅极的第一区域和具有多个第二栅极的第二区域的衬底，其中相邻的第一栅极和相邻的第二栅极由绝缘体隔开，并且顶部 绝缘体的表面具有多个凹部。 然后，在第一栅极，第二栅极和绝缘体上形成覆盖层，并填充凹部。 去除覆盖层直到达到绝缘体的顶表面，从而形成填充凹部的绝缘沉积物，其中绝缘沉积物的上表面基本上与绝缘体的顶表面对准。