公开(公告)号：US06285203B1

公开(公告)日：2001-09-04

申请号：US09332838

申请日：1999-06-14

申请人： Salman Akram ,  Warren M. Farnworth ,  Michael E. Hess ,  David R. Hembree

发明人： Salman Akram ,  Warren M. Farnworth ,  Michael E. Hess ,  David R. Hembree

IPC分类号： G01R102

CPC分类号： G01R1/0483 ,  G01R31/2886 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/8592 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/15312 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00

摘要： A test system for testing semiconductor components includes an interconnect having contacts for making temporary electrical connections with terminal contacts on the components. The interconnect contacts can be configured to electrically engage planar terminal contacts (e.g., bond pads, test pads) or bumped terminal contacts (e.g., solder bumps, solder balls) on the components. The test system also includes an alignment member for aligning the components to the interconnect. Different embodiments of the alignment member include: a curable polymer material molded in place on the interconnect; an alignment opening formed as an etched pocket in a substrate of the interconnect; and a separate fence attached to the interconnect using an alignment fixture.

公开(公告)号：US06255833B1

公开(公告)日：2001-07-03

申请号：US09098594

申请日：1998-06-17

申请人： Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  Warren M. Farnworth

发明人： Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  Warren M. Farnworth

IPC分类号： G01R3102

CPC分类号： G01R1/0483 ,  H01L2224/48091 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/30107 ,  H01L2924/00014

摘要： A method and carrier for testing semiconductor dice such as bare dice or chip scale packages are provided. The carrier includes a base for retaining a single die, an interconnect for establishing temporary electrical communication with the die, and a force applying mechanism for biasing the die and interconnect together. In an illustrative embodiment the base includes conductors arranged in a universal pattern adapted to electrically connect to different sized interconnects. Interconnects are thus interchangeable on a base for testing different types of dice using the same base. The conductors on the base can be formed on a planar active surface of the base or on a stepped active surface having different sized cavities for mounting different sized interconnects. In an alternate embodiment the carrier includes an interposer. In a first interposer embodiment, the interposer connects directly to external test circuitry and can be changed to accommodate different sized interconnects. In a second interposer embodiment, the interposer connects to conductors on the base and adapts the base for use with different sized interconnects.

摘要翻译： 提供了用于测试半导体裸片（例如裸裸片或芯片级封装）的方法和载体。 载体包括用于保持单个管芯的基座，用于建立与管芯的临时电连通的互连件，以及用于偏压管芯并互连在一起的施力机构。 在说明性实施例中，底座包括以适于电连接到不同尺寸的互连件的通用图案布置的导体。 因此，互连在基座上可以互换，用于使用相同的基底测试不同类型的骰子。 基座上的导体可以形成在基座的平面有源表面上或具有不同尺寸的空腔的阶梯式有源表面上，用于安装不同尺寸的互连。在替代实施例中，载体包括插入器。 在第一插入器实施例中，插入器直接连接到外部测试电路，并且可以改变以适应不同尺寸的互连。 在第二插入器实施例中，插入器连接到基座上的导体，并使基座适配于不同大小的互连使用。

公开(公告)号：US06204678B1

公开(公告)日：2001-03-20

申请号：US09302833

申请日：1999-04-30

申请人： Salman Akram ,  James M. Wark ,  Warren M. Farnworth

发明人： Salman Akram ,  James M. Wark ,  Warren M. Farnworth

IPC分类号： G01R173

CPC分类号： G01R31/2886 ,  G01R1/0408

摘要： An interconnect and system for testing semiconductor dice, and a test method using the interconnect are provided. The interconnect includes a substrate having patterns of contact members for electrically contacting the dice. The interconnect also includes patterns of conductors for providing electrical paths to the contact members. In addition, the interconnect includes contact receiving cavities configured to retain electrical connectors of a testing apparatus in electrical communication with the conductors. A die level test system includes the interconnect mounted to a temporary package for a singulated die. In the die level test system, the interconnect provides direct electrical access from testing circuitry to the die. A wafer level test system includes the interconnect mounted to a probe card fixture of a wafer probe handler. In the wafer level test system, the contact receiving cavities can be configured to support and align the interconnect to the probe card fixture.

摘要翻译： 提供了用于测试半导体晶片的互连和系统，以及使用该互连的测试方法。 互连包括具有用于电接触骰子的接触构件图案的衬底。 互连还包括用于向接触构件提供电路径的导体图案。 此外，互连件包括被配置为保持与导体电连通的测试装置的电连接器的接触接收腔。 芯片级测试系统包括安装到用于单个模具的临时封装的互连。 在芯片级测试系统中，互连提供从测试电路到芯片的直接电接入。 晶片级测试系统包括安装到晶片探测器处理器的探针卡夹具上的互连。 在晶片级测试系统中，触点接收腔可以被配置为支撑并将互连对准到探针卡固定装置。

公开(公告)号：US06025730A

公开(公告)日：2000-02-15

申请号：US818456

申请日：1997-03-17

申请人： Salman Akram ,  James M. Wark ,  Warren M. Farnworth

发明人： Salman Akram ,  James M. Wark ,  Warren M. Farnworth

IPC分类号： G01R1/04 ,  G01R31/28 ,  G01R1/73

CPC分类号： G01R31/2886 ,  G01R1/0408

摘要： An interconnect and system for testing semiconductor dice, and a test method using the interconnect are provided. The interconnect includes a substrate having patterns of contact members for electrically contacting the dice. The interconnect also includes patterns of conductors for providing electrical paths to the contact members. In addition, the interconnect includes contact receiving cavities configured to retain electrical connectors of a testing apparatus in electrical communication with the conductors. A die level test system includes the interconnect mounted to a temporary package for a singulated die. In the die level test system, the interconnect provides direct electrical access from testing circuitry to the die. A wafer level test system includes the interconnect mounted to a probe card fixture of a wafer probe handler. In the wafer level test system, the contact receiving cavities can be configured to support and align the interconnect to the probe card fixture.

摘要翻译： 提供了用于测试半导体晶片的互连和系统，以及使用该互连的测试方法。 互连包括具有用于电接触骰子的接触构件图案的衬底。 互连还包括用于向接触构件提供电路径的导体图案。 此外，互连件包括被配置为保持与导体电连通的测试装置的电连接器的接触接收腔。 芯片级测试系统包括安装到用于单个模具的临时封装的互连。 在芯片级测试系统中，互连提供从测试电路到芯片的直接电接入。 晶片级测试系统包括安装到晶片探测器处理器的探针卡夹具上的互连。 在晶片级测试系统中，触点接收腔可以被配置为支撑并将互连对准到探针卡固定装置。

公开(公告)号：US07960829B2

公开(公告)日：2011-06-14

申请号：US11216617

申请日：2005-08-31

申请人： Alan G. Wood ,  Warren M. Farnworth ,  David R. Hembree ,  Sidney B. Rigg ,  William M. Hiatt ,  Peter Benson ,  Kyle K. Kirby ,  Salman Akram

发明人： Alan G. Wood ,  Warren M. Farnworth ,  David R. Hembree ,  Sidney B. Rigg ,  William M. Hiatt ,  Peter Benson ,  Kyle K. Kirby ,  Salman Akram

IPC分类号： H01L23/12

CPC分类号： G03F7/0037 ,  B33Y30/00 ,  B33Y70/00 ,  B33Y80/00 ,  G03F7/0047

摘要： A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion that extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member that substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface.

摘要翻译： 用于半导体衬底的减薄或后研磨以及在半导体衬底的后变薄处理期间的支撑结构包括基本上沿着半导体衬底的外周延伸并围绕半导体衬底的外周延伸的部分，以使半导体衬底 基板具有刚性。 支撑结构可以被构造为环或作为基本上覆盖半导体衬底的有源表面并且在由有源表面承载的每个半导体器件上形成保护结构的构件。

公开(公告)号：US07531453B2

公开(公告)日：2009-05-12

申请号：US12027106

申请日：2008-02-06

申请人： Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

发明人： Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/09827 ,  H05K2203/072 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

摘要翻译： 本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微电子器件中形成互连的方法。 在一个实施例中，一种方法包括提供具有正面和背面的微电子衬底。 衬底具有包括集成电路的微电子管芯和可操作地耦合到集成电路的端子。 该方法还包括至少部分地形成通过基底并且在基底的前侧和/或后侧具有开口的通道。 该方法还包括用封闭通道一端的导电盖密封开口，同时通道的另一端保持打开。 该方法然后包括用导电材料填充通道。

公开(公告)号：US06417685B1

公开(公告)日：2002-07-09

申请号：US10045420

申请日：2002-01-15

申请人： Salman Akram ,  Warren M. Farnworth ,  Michael E. Hess ,  David R. Hembree

发明人： Salman Akram ,  Warren M. Farnworth ,  Michael E. Hess ,  David R. Hembree

IPC分类号： G01R3126

CPC分类号： G01R1/0483 ,  G01R31/2886 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/8592 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/15312 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00

摘要： A test system for testing semiconductor components includes an interconnect having contacts for making temporary electrical connections with terminal contacts on the components. The interconnect contacts can be configured to electrically engage planar terminal contacts (e.g., bond pads, test pads) or bumped terminal contacts (e.g., solder bumps, solder balls) on the components. The test system also includes an alignment member for aligning the components to the interconnect. Different embodiments of the alignment member include: a curable polymer material molded in place on the interconnect; an alignment opening formed as an etched pocket in a substrate of the interconnect; and a separate fence attached to the interconnect using an alignment fixture.

摘要翻译： 用于测试半导体部件的测试系统包括具有用于与组件上的端子触点进行临时电连接的触点的互连。 互连触点可以被配置为电连接部件上的平面端子触头（例如，接合焊盘，测试焊盘）或凸起的端子触头（例如，焊料凸块，焊球）。 测试系统还包括用于将部件对准互连的对准部件。 对准构件的不同实施例包括：在互连上模制就位的可固化聚合物材料; 在所述互连的基板中形成作为蚀刻袋的对准开口; 以及使用对准夹具附接到互连件的单独的栅栏。

公开(公告)号：US06207548B1

公开(公告)日：2001-03-27

申请号：US08811711

申请日：1997-03-05

申请人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth

发明人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth

IPC分类号： H01L2144

CPC分类号： H01L23/13 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/1148 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13339 ,  H01L2224/16237 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/29099 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/013

摘要： A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array, or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.

摘要翻译： 芯片级封装由半导体管芯组成，半导体管芯具有层压在其有源表面上的硅片。 模具的接合焊盘通过微机械加工通过坯件的孔进入。 该封装可以与引线接合使用，或者可以将焊料或其它导电凸块放置在用于倒装芯片应用的空白孔中。 此外，封装可以用于将管芯的外部连接重新路由到其他位置，例如集中式球栅阵列，或用于直接或离散管芯连接（DDC）到载体的边缘连接装置。 优选的是，芯片级封装形成在晶片级，作为如此形成的多个封装之一，其形成有晶片级坯料，并且整个晶片被烧入并测试以识别已知的良好裸片（KGD ），然后将晶片层压板分离成单个包装。

公开(公告)号：US6072236A

公开(公告)日：2000-06-06

申请号：US612059

申请日：1996-03-07

申请人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth

发明人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/13 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/1148 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13339 ,  H01L2224/16237 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043

摘要： A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.

公开(公告)号：US6016060A

公开(公告)日：2000-01-18

申请号：US823490

申请日：1997-03-25

申请人： Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  David R. Hembree

发明人： Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  David R. Hembree

IPC分类号： G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R31/28 ,  G01R31/26

CPC分类号： G01R1/0466

摘要： A method, apparatus and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The apparatus includes an interconnect having patterns of contact members adapted to electrically contact the contact bumps. Each contact member includes an array of one or more electrically conductive projections in electrical communication with an associated conductor. The projections form contact members for retaining individual contact bumps on the semiconductor components. The projections can be pillars having angled faces covered with a conductive layer. Alternately the projections can be a material deposited on the substrate, or can be microbumps formed on multi layered tape bonded to the substrate. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.