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    Probe card for semiconductor wafers having mounting plate and socket
    3.
    发明授权
    Probe card for semiconductor wafers having mounting plate and socket 失效
    带安装板和插座的半导体晶圆探头卡

    公开(公告)号：US07250780B2

    公开(公告)日：2007-07-31

    申请号：US10742729

    申请日：2003-12-19

    申请人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

    发明人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

    IPC分类号： G01R1/073 ,  G01R31/28

    CPC分类号： G01R31/2886

    摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.

    摘要翻译： 提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。 探针卡被配置用于与测试电路电气通信的常规测试装置，例如晶片探测器处理器。 探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。 探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。 互连衬底可以由具有穿透突起的凸起接触构件的硅形成。 或者，接触构件可以形成为用于测试凸起的晶片的凹陷。 膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。 探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

    Carrier and system for testing bumped semiconductor components
    5.
    发明授权
    Carrier and system for testing bumped semiconductor components 失效
    用于测试碰撞半导体元件的载体和系统

    公开(公告)号：US06313651B1

    公开(公告)日：2001-11-06

    申请号：US09322724

    申请日：1999-05-28

    申请人： David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  Salman Akram

    发明人： David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  Salman Akram

    IPC分类号： G01R3102

    CPC分类号： G01R1/0483 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/48091 ,  H01L2224/81385 ,  H01L2924/01021 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10155 ,  H01L2924/15311 ,  H01L2924/00014

    摘要： A semiconductor carrier and system for testing bumped semiconductor components, such as dice and packages, having contact bumps are provided. The carrier includes a base, an interconnect, and a force applying mechanism. The interconnect includes patterns of contact members adapted to electrically contact the contact bumps. The interconnect can include a substrate having contact members formed as recesses, or as projections, covered with conductive layers. Alternately, the interconnect can be a multi layered tape bonded directly to a base of the carrier. In addition to providing electrical connections, the contact members perform an alignment function by self centering the contact bumps within the contact members. The carrier can also include an alignment member configured to align the components with the interconnect. The system can include the carrier, a socket, and a testing apparatus such as a burn-in board in electrical communication with test circuitry.

    摘要翻译： 提供了一种半导体载体和系统，用于测试具有接触凸块的凸起的半导体部件，例如芯片和封装。 载体包括基底，互连和力施加机构。 互连包括适于电接触接触凸块的接触构件的图案。 互连可以包括具有形成为凹陷的接触构件的衬底，或者作为突出部的覆盖有导电层的衬底。 或者，互连可以是直接结合到载体的基底的多层带。 除了提供电连接之外，接触构件通过使接触构件内的接触凸块自对中来执行对准功能。 载体还可以包括配置成将部件与互连对准的对准部件。 该系统可以包括载体，插座和诸如与测试电路电连接的老化板的测试装置。

    Method for testing semiconductor dice and chip scale packages
    6.
    发明授权
    Method for testing semiconductor dice and chip scale packages 失效
    半导体芯片和芯片级封装的测试方法

    公开(公告)号：US06255833B1

    公开(公告)日：2001-07-03

    申请号：US09098594

    申请日：1998-06-17

    申请人： Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  Warren M. Farnworth

    发明人： Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  Warren M. Farnworth

    IPC分类号： G01R3102

    CPC分类号： G01R1/0483 ,  H01L2224/48091 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/30107 ,  H01L2924/00014

    摘要： A method and carrier for testing semiconductor dice such as bare dice or chip scale packages are provided. The carrier includes a base for retaining a single die, an interconnect for establishing temporary electrical communication with the die, and a force applying mechanism for biasing the die and interconnect together. In an illustrative embodiment the base includes conductors arranged in a universal pattern adapted to electrically connect to different sized interconnects. Interconnects are thus interchangeable on a base for testing different types of dice using the same base. The conductors on the base can be formed on a planar active surface of the base or on a stepped active surface having different sized cavities for mounting different sized interconnects. In an alternate embodiment the carrier includes an interposer. In a first interposer embodiment, the interposer connects directly to external test circuitry and can be changed to accommodate different sized interconnects. In a second interposer embodiment, the interposer connects to conductors on the base and adapts the base for use with different sized interconnects.

    摘要翻译： 提供了用于测试半导体裸片（例如裸裸片或芯片级封装）的方法和载体。 载体包括用于保持单个管芯的基座，用于建立与管芯的临时电连通的互连件，以及用于偏压管芯并互连在一起的施力机构。 在说明性实施例中，底座包括以适于电连接到不同尺寸的互连件的通用图案布置的导体。 因此，互连在基座上可以互换，用于使用相同的基底测试不同类型的骰子。 基座上的导体可以形成在基座的平面有源表面上或具有不同尺寸的空腔的阶梯式有源表面上，用于安装不同尺寸的互连。在替代实施例中，载体包括插入器。 在第一插入器实施例中，插入器直接连接到外部测试电路，并且可以改变以适应不同尺寸的互连。 在第二插入器实施例中，插入器连接到基座上的导体，并使基座适配于不同大小的互连使用。

    Apparatus for testing semiconductor wafers
    7.
    发明授权
    Apparatus for testing semiconductor wafers 有权
    半导体晶片测试装置

    公开(公告)号：US6064216A

    公开(公告)日：2000-05-16

    申请号：US241553

    申请日：1999-02-01

    申请人： Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  James M. Wark ,  John O. Jacobson

    发明人： Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  James M. Wark ,  John O. Jacobson

    IPC分类号： G01R1/04 ,  G01R31/28 ,  G01R31/02

    CPC分类号： G01R1/0491 ,  G01R31/2886

    摘要： A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.

    摘要翻译： 提供了一种用于测试半导体晶片的方法，装置和系统。 该方法包括提供晶片载体以提供用于接收和传输测试信号到晶片的电路径。 晶片载体包括用于保持晶片的基座和具有被配置为与晶片上的接触位置建立电连通的接触构件的互连。 晶片载体可以包括被配置为偏置晶片并在组装的载体中互连在一起的一个或多个可压缩弹簧构件。 可以使用光学对准技术来组装晶片载体，其中晶片与互连对准，以及类似于用于倒装芯片接合半导体晶片的对准器焊接工具的组装工具。 与载体一起使用的系统可以包括测试装置，其被配置为在晶片受到温度循环的同时将测试信号通过载体施加到晶片。

    System and interconnect for making temporary electrical connections with bumped semiconductor components
    8.
    发明授权
    System and interconnect for making temporary electrical connections with bumped semiconductor components 有权
    用于与凸起的半导体部件进行临时电连接的系统和互连

    公开(公告)号：US5915977A

    公开(公告)日：1999-06-29

    申请号：US138612

    申请日：1998-08-24

    申请人： David R. Hembree ,  John O. Jacobson ,  James M. Wark ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood

    发明人： David R. Hembree ,  John O. Jacobson ,  James M. Wark ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood

    IPC分类号： G01R1/04 ,  H01L21/00 ,  H01R12/04 ,  H05K3/32 ,  H01R9/09

    CPC分类号： H01L21/67144 ,  G01R1/0408 ,  H05K3/326 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81385

    摘要： An interconnect and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The interconnect includes a substrate with patterns of contact members adapted to electrically contact the contact bumps. The substrate can be formed of a material such as ceramic, silicon, FR-4, or photo-chemically machineable glass. The contact members can be formed as recesses covered with conductive layers in electrical communication with conductors and terminal contacts on the substrate. Alternately, the contact members can be formed as projections adapted to penetrate the contact bumps, as microbumps with a rough textured surface, or as a deposited layer formed with recesses. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.

    摘要翻译： 提供了一种用于与具有接触凸块的半导体部件建立临时电连通的互连和系统。 互连包括具有适于电接触接触凸块的接触部件图案的基板。 衬底可由诸如陶瓷，硅，FR-4或光刻化学可加工玻璃的材料形成。 接触构件可以形成为覆盖有与衬底上的导体和端子触点电连通的导电层的凹陷。 或者，接触构件可以形成为适于穿透接触凸块的突起，作为具有粗糙纹理表面的微胶囊，或者形成为具有凹陷的沉积层。 互连可以用于晶片级测试系统中，用于测试包含在晶片上的骰子，或者用于测试裸露的骰子或凸起的芯片级封装的芯片级测试系统。

    Methods for thinning semiconductor substrates that employ support structures formed on the substrates
    10.
    发明授权
    Methods for thinning semiconductor substrates that employ support structures formed on the substrates 有权
    减薄采用在基板上形成的支撑结构的半导体衬底的方法

    公开(公告)号：US07713841B2

    公开(公告)日：2010-05-11

    申请号：US10666742

    申请日：2003-09-19

    申请人： Alan G. Wood ,  Warren M. Farnworth ,  David R. Hembree ,  Sidney B. Rigg ,  William M. Hiatt ,  Peter Benson ,  Kyle K. Kirby ,  Salman Akram

    发明人： Alan G. Wood ,  Warren M. Farnworth ,  David R. Hembree ,  Sidney B. Rigg ,  William M. Hiatt ,  Peter Benson ,  Kyle K. Kirby ,  Salman Akram

    IPC分类号： H01L21/46

    CPC分类号： G03F7/0037 ,  B33Y30/00 ,  B33Y70/00 ,  B33Y80/00 ,  G03F7/0047

    摘要： A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion which extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member which substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface. Assemblies that include the support structure and a semiconductor substrate are also within the scope of the present invention, as are methods for forming the support structures and thinning and post-thinning processes that include use of the support structures.

    摘要翻译： 在半导体衬底的薄化或后研磨以及后稀化处理期间与半导体衬底一起使用的支撑结构包括基本上沿半导体衬底的外周延伸并且围绕半导体衬底的外周延伸的部分，以使薄化半导体 基板具有刚性。 支撑结构可以被配置为环或作为基本上覆盖半导体衬底的有源表面并且在由有源表面承载的每个半导体器件上形成保护结构的构件。 包括支撑结构和半导体衬底的组件也在本发明的范围内，形成支撑结构的方法和包括使用支撑结构的减薄和后变薄工艺也是如此。