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    NOVEL COMPUTING SYSTEM
    61.
    发明申请
    NOVEL COMPUTING SYSTEM 审中-公开
    新型计算系统

    公开(公告)号：US20140059411A1

    公开(公告)日：2014-02-27

    申请号：US13593895

    申请日：2012-08-24

    申请人： Zvi Or-Bach ,  Ze'ev Wurman ,  Brian Cronquist

    发明人： Zvi Or-Bach ,  Ze'ev Wurman ,  Brian Cronquist

    IPC分类号： G06F17/21

    CPC分类号： G06F17/211 ,  G06F16/5846 ,  G06F17/2235 ,  G06F17/2765

    摘要： A computing system including a processor, display, pointing device and memory; wherein the memory includes a text file, a graphics file corresponding to said text file and executable instructions to perform at least these actions (i) identify a selection of an alphanumeric identifier within a displayed text file, and then (ii) identify the appearance of the identifier in a corresponding graphics file, and then (iii) display a page of the graphics file comprising the appearance of the identifier.

    摘要翻译： 一种包括处理器，显示器，指示装置和存储器的计算系统; 其中所述存储器包括文本文件，对应于所述文本文件的图形文件和至少执行这些动作的可执行指令（i）识别显示的文本文件内的字母数字标识符的选择，然后（ii）识别 相应图形文件中的标识符，然后（iii）显示包括标识符的外观的图形文件的页面。

    SEMICONDUCTOR DEVICE AND STRUCTURE FOR HEAT REMOVAL
    64.
    发明申请
    SEMICONDUCTOR DEVICE AND STRUCTURE FOR HEAT REMOVAL 有权
    半导体器件和热解决结构

    公开(公告)号：US20120306082A1

    公开(公告)日：2012-12-06

    申请号：US13571614

    申请日：2012-08-10

    申请人： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

    发明人： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

    IPC分类号： H01L23/50

    CPC分类号： H01L23/3677 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/11807 ,  H01L27/12 ,  H01L29/785 ,  H01L2027/11812 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device, including: a first layer of first transistors, overlaid by at least one interconnection layer, wherein the interconnection layer includes metals such as copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, wherein the second layer is less than about 0.4 micron thick; and a connection path connecting the second transistors to the interconnection layer, wherein the connection path includes at least one through-layer via, and the through-layer via includes material whose co-efficient of thermal expansion is within about 50 percent of the second layer coefficient of thermal expansion.

    摘要翻译： 一种器件，包括：由至少一个互连层覆盖的第一晶体管层，其中所述互连层包括诸如铜或铝的金属; 包括第二晶体管的第二层，所述第二层覆盖所述互连层，其中所述第二层小于约0.4微米厚; 以及将所述第二晶体管连接到所述互连层的连接路径，其中所述连接路径包括至少一个通孔，并且所述贯通层通孔包括其热膨胀系数在所述第二层的约50％内的材料 热膨胀系数。

    3D SEMICONDUCTOR DEVICES AND STRUCTURES
    65.
    发明申请
    3D SEMICONDUCTOR DEVICES AND STRUCTURES 有权

    公开(公告)号：US20210242189A1

    公开(公告)日：2021-08-05

    申请号：US17151867

    申请日：2021-01-19

    申请人： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    发明人： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC分类号： H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/473 ,  H01L21/768 ,  H01L25/00

    摘要： A 3D device, the first level including first transistors and a first interconnect; a second level with second transistors overlaying the first level; a third level with third transistors overlaying the second level; a plurality of electronic circuit units (ECUs), where each ECU includes a first circuit with a portion of the first transistors, where each of the ECUs includes a second circuit including a portion of the second transistors, where each of the plurality of ECUs includes a third circuit, which includes a portion of the third transistors, where each of the ECUs includes a vertical data bus, where the vertical data bus has between eight pillars and three hundreds pillars, where the vertical data bus provides electrical connections between the first and second circuits, where the third level includes an array of memory cells, and where the second circuit includes a memory control circuit.

    Semiconductor device and structure for heat removal
    66.
    发明授权
    Semiconductor device and structure for heat removal 有权
    半导体器件和结构的散热

    公开(公告)号：US08450804B2

    公开(公告)日：2013-05-28

    申请号：US13571614

    申请日：2012-08-10

    申请人： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

    发明人： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

    CPC分类号： H01L23/3677 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/11807 ,  H01L27/12 ,  H01L29/785 ,  H01L2027/11812 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device, including: a first layer of first transistors, overlaid by at least one interconnection layer, wherein the interconnection layer includes metals such as copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, wherein the second layer is less than about 0.4 micron thick; and a connection path connecting the second transistors to the interconnection layer, wherein the connection path includes at least one through-layer via, and the through-layer via includes material whose co-efficient of thermal expansion is within about 50 percent of the second layer coefficient of thermal expansion.

    摘要翻译： 一种器件，包括：由至少一个互连层覆盖的第一晶体管层，其中所述互连层包括诸如铜或铝的金属; 包括第二晶体管的第二层，所述第二层覆盖所述互连层，其中所述第二层小于约0.4微米厚; 以及将所述第二晶体管连接到所述互连层的连接路径，其中所述连接路径包括至少一个通孔，并且所述贯通层通孔包括其热膨胀系数在所述第二层的约50％内的材料 热膨胀系数。

    Method for fabrication of a semiconductor element and structure thereof
    67.
    发明授权
    Method for fabrication of a semiconductor element and structure thereof 有权
    半导体元件的制造方法及其结构

    公开(公告)号：US08390326B2

    公开(公告)日：2013-03-05

    申请号：US12782448

    申请日：2010-05-18

    申请人： Zvi Or-Bach ,  James M. Tour ,  Jun Yao ,  Brian Cronquist

    发明人： Zvi Or-Bach ,  James M. Tour ,  Jun Yao ,  Brian Cronquist

    IPC分类号： H03K19/177

    CPC分类号： H01L23/5252 ,  H01L23/53276 ,  H01L27/11803 ,  H01L2924/0002 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1778 ,  H03K19/17796 ,  H01L2924/00

    摘要： Re-programmable antifuses and structures utilizing re-programmable antifuses are presented herein. Such structures include a configurable interconnect circuit having at least one re-programmable antifuse, wherein the at least one re-programmable antifuse is configured to be programmed to conduct by applying a first voltage across it and is configured to be re-programmed not to conduct by applying second voltage across it, wherein the second voltage is higher than the first voltage. Additionally, the re-programmable antifuses may be configured to a permanently conductive state by applying an even higher voltage across it.

    摘要翻译： 本文介绍了使用可重新编程反熔丝的可重新编程反熔丝和结构。 这种结构包括具有至少一个可再编程反熔丝的可配置互连电路，其中所述至少一个可再编程反熔丝被配置为通过在其上施加第一电压而被编程为进行导通，并被配置为被重新编程为不进行 通过在其上施加第二电压，其中第二电压高于第一电压。 此外，重编程反熔丝可以通过在其上施加更高的电压而被配置为永久导通状态。

    3D semiconductor device(s) and structure(s) with electronic control units
    69.
    发明授权
    3D semiconductor device(s) and structure(s) with electronic control units 有权

    公开(公告)号：US11270988B2

    公开(公告)日：2022-03-08

    申请号：US17151867

    申请日：2021-01-19

    申请人： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    发明人： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/473 ,  H01L21/768 ,  H01L25/00 ,  H01L25/065

    摘要： A 3D device, the first level including first transistors and a first interconnect; a second level with second transistors overlaying the first level; a third level with third transistors overlaying the second level; a plurality of electronic circuit units (ECUs), where each ECU includes a first circuit with a portion of the first transistors, where each of the ECUs includes a second circuit including a portion of the second transistors, where each of the plurality of ECUs includes a third circuit, which includes a portion of the third transistors, where each of the ECUs includes a vertical data bus, where the vertical data bus has between eight pillars and three hundreds pillars, where the vertical data bus provides electrical connections between the first and second circuits, where the third level includes an array of memory cells, and where the second circuit includes a memory control circuit.