公开(公告)号：US20030002546A1

公开(公告)日：2003-01-02

申请号：US10180032

申请日：2002-06-27

申请人： Fujitsu Quantum Devices Limited

发明人： Haruyoshi Ono ,  Isao Baba

IPC分类号： H01S003/10

CPC分类号： H01S5/0687 ,  H01S5/0612 ,  H01S5/0617

摘要： In order to tune an oscillation wavelength of a semiconductor laser diode to a target wavelength, the amount of change of a wavelength to the amount of change of a wavelength varying item is determined by actual measurement and a basic wavelength coefficient is renewed by using the ratio of both amounts of change as a corrective wavelength coefficient, and thus the characteristic when the wavelength of an actual device is made closer to a target wavelength is utilized.

摘要翻译： 为了将半导体激光二极管的振荡波长调谐到目标波长，通过实际测量确定波长变化量的变化量，并且通过使用比率来更新基本波长系数 作为校正波长系数的两个变化量，并且因此利用当使实际装置的波长更接近目标波长时的特性。

公开(公告)号：US20020180005A1

公开(公告)日：2002-12-05

申请号：US10156955

申请日：2002-05-30

申请人： Fujitsu Quantum Devices Limited

发明人： Hitoshi Haematsu

IPC分类号： H01L029/40

CPC分类号： H01L29/4175 ,  H01L21/768 ,  H01L23/481 ,  H01L23/4824 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/812 ,  H01L2924/0002 ,  Y10T29/49087 ,  H01L2924/00

摘要： A source electrode, a gate electrode, and a drain electrode formed on a front face active region of a semiconductor substrate in a shape of teeth of a comb are covered with an insulating film such as polyimede etc., as well as all of the upper surface and the side surfaces of the insulating film are covered with a metal protective film. Via hole receiving pads connected to the source electrode, the gate electrode, and the drain electrode are respectively connected to bonding pads on a reveres face of the semiconductor substrate through via holes.

摘要翻译： 形成在梳齿形状的半导体基板的正面有源区域上的源电极，栅电极和漏电极被绝缘膜覆盖，例如聚酰亚胺等，以及所有的上部 表面和绝缘膜的侧表面被金属保护膜覆盖。 连接到源电极，栅电极和漏电极的通孔接收焊盘分别通过通孔连接到半导体衬底的表面上的接合焊盘。

公开(公告)号：US20020140041A1

公开(公告)日：2002-10-03

申请号：US10092308

申请日：2002-03-07

申请人： Fujitsu Quantum Devices Limited

发明人： Hiroshi Endoh

IPC分类号： H01L029/76

CPC分类号： H01L29/66878 ,  H01L29/66318 ,  H01L29/7371

摘要： An edge of a passivation film is positioned inside an edge of an overhanging emitter structure by a distance L so that a base electrode layer is formed at an interval not to overlap the edge of the passivation film even when the base electrode layer is formed by etching with the emitter structure as a mask.

摘要翻译： 钝化膜的边缘位于突出的发射极结构的边缘内部距离L，使得即使当通过蚀刻形成基极层时，基板电极层以不与钝化膜的边缘重叠的间隔形成 以发射器结构为掩模。

公开(公告)号：US20020127759A1

公开(公告)日：2002-09-12

申请号：US09946686

申请日：2001-09-06

申请人： Fujitsu Quantum Devices Limited

发明人： Takayuki Watanabe

IPC分类号： H01L021/00

CPC分类号： H01L31/0304 ,  H01L31/02019 ,  H01L31/173 ,  H01L31/184 ,  H01L33/0062 ,  H01S5/026 ,  H01S5/2275 ,  H01S5/305 ,  H01S5/3077 ,  H01S5/3202 ,  Y02E10/544

摘要： An n type InP buried layer 22 with Se or S added in an above 5null1018 cmnull3 concentration is formed on an active layer mesa stripe 18 having a surface with an SiO2 film 16 formed on at a peripheral part of the mesa stripe 18 other than the surface with the SiO2 film 16 formed on. Accordingly, the buried layer can be grown without the over growth.

摘要翻译： 在具有表面的有源层台面条18上形成具有以5×10 18 cm -3以上添加的Se或S的n型InP掩埋层22，其中SiO 2膜16形成在台面条18的周边部分之外， 形成有SiO 2膜16的表面。 因此，埋层可以在没有过度生长的情况下生长。

公开(公告)号：US20020094677A1

公开(公告)日：2002-07-18

申请号：US10044979

申请日：2002-01-15

申请人： Fujitsu Quantum Devices Limited

发明人： Akira Furuya ,  Chikashi Anayama ,  Katsumi Sugiura ,  Kensei Nakao ,  Taro Hasegawa

IPC分类号： H01L021/44

CPC分类号： B82Y20/00 ,  H01L21/02395 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/0262 ,  H01S5/2201 ,  H01S5/2238 ,  H01S5/305 ,  H01S5/3054 ,  H01S5/34326 ,  H01S5/3436 ,  H01S2301/173 ,  H01S2304/04

摘要： In the S3-type semiconductor laser, when an angle of a first growth profile line to the first principal plane, the first growth profile line connecting respective lower side lines of an upper inclined plane and a lower inclined plane of the first layer of the first conduction type cladding layer is null1, an angle of a second growth profile line to the first principal plane, the second growth profile line connecting respective lower side lines of an upper inclined plane and a lower inclined plane of the second layer of the first conduction type cladding layer is null2, an angle of a third growth profile line to the first principal plane, the third growth profile line connecting respective lower side lines of an upper inclined plane and a lower inclined plane of the third layer of the first conduction type cladding layer is null3, and an angle of a fourth growth profile line to the first principal plane, the fourth growth profile line connecting respective lower side lines of an upper inclined plane and a lower inclined plane of the fourth layer of the first conduction type cladding layer is null4, relationships null1 null3, null3

公开(公告)号：US20020024411A1

公开(公告)日：2002-02-28

申请号：US09903811

申请日：2001-07-13

申请人： Fujitsu Quantum Devices Limited

发明人： Hideyuki Uchino

IPC分类号： H04B001/26

CPC分类号： H03B19/14

摘要： A branching section provides a fundamental input wave signal SI of a frequency f to the gate of a FET 15A having a grounded source and the source of a FET 15B having an AC grounded gate, and a signal joining section synthesizes the output signals of the FETs 15A and 15B. An open stub 24 as an amplitude attenuating element is connected to a transmission line 19B of the signal joining section. The length of the open stub 24 is not an integral multiply of null/4, where null denotes the wavelength of the fundamental signal SI, and adjusted in simulation such that an amplitude difference between second harmonics included in the drain voltage signals SD1 and SD2 of the respective FETs 15A and 15B is reduced to almost zero. Although the open stub 24 itself is a phase compensating element, since the transfer characteristic of the FET 15B changes by connecting the open stub 24 to the transmission line 19B, the open stub 24 works as an amplitude attenuating element.

摘要翻译： 分支部分提供具有接地源的FET 15A的栅极的频率f的基本输入波信号SI和具有交流接地栅极的FET 15B的源极，并且信号接合部分合成FET的输出信号 图15A和15B。 作为振幅衰减元件的开路短截线24连接到信号接合部的传输线19B。 开路短线24的长度不是lambd / 4的整数乘法，其中lambd表示基本信号SI的波长，并且在模拟中调整，使得包括在漏极电压信号SD1和SD2中的二次谐波之间的振幅差为 相应的FET 15A和15B减小到几乎为零。 虽然开路短截线24本身是相位补偿元件，但是由于通过将开路短截线24连接到传输线19B来改变FET 15B的传递特性，因此开路短截线24作为振幅衰减元件工作。

公开(公告)号：US20020013033A1

公开(公告)日：2002-01-31

申请号：US09774583

申请日：2001-02-01

申请人： Fujitsu Quantum Devices Limited

发明人： Jun Wada

IPC分类号： H01L021/331 ,  H01L021/8222 ,  H01L031/0328 ,  H01L031/0336 ,  H01L031/072 ,  H01L031/109

CPC分类号： H01L29/66318 ,  H01L27/0658 ,  H01L29/7371

摘要： A semiconductor integrated circuit device comprises an active device and a resistance element formed monolithically on a common substrate wherein the resistance element includes a dummy pattern having a layered structure identical with a layered structure of the active device, and first and second electrodes are provided inside a mesa structure provided for the resistance element with a separation from a sidewall of the mesa structure, the first and second electrodes being formed in correspondence to openings formed in the dummy pattern.

摘要翻译： 半导体集成电路器件包括有源器件和在公共衬底上一体形成的电阻元件，其中电阻元件包括具有与有源器件的分层结构相同的分层结构的虚拟图案，并且第一和第二电极设置在 所述电阻元件与所述台面结构的侧壁分离设置的所述台面结构，所述第一和第二电极对应于形成在所述虚拟图案中的开口形成。

公开(公告)号：US6037245A

公开(公告)日：2000-03-14

申请号：US340193

申请日：1999-06-28

申请人： Hajime Matsuda

发明人： Hajime Matsuda

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L21/335 ,  H01L21/338 ,  H01L21/768 ,  H01L29/40 ,  H01L21/3205

CPC分类号： H01L29/66878 ,  H01L21/28587 ,  H01L29/66462 ,  H01L21/7682 ,  H01L28/10

摘要： A fabricating process of a semiconductor device includes the steps of forming a first photoresist layer on a surface of a substrate so as to cover a gate electrode on the substrate, forming a second photoresist layer on the fist photoresist layer with an increased sensitivity, forming a third photoresist layer on the second photoresist layer with a reduced sensitivity, forming an opening in a photoresist structure thus formed of the first through third photoresist layers such that the opening exposes the gate electrode and such that the opening has a diameter that increases gradually from the first photoresist layer to the second photoresist layer. Further, a low-resistance metal layer is deposited on the photoresist structure including the opening, such that the metal layer forms a low-resistance electrode on the gate electrode.

摘要翻译： 半导体器件的制造方法包括以下步骤：在衬底的表面上形成第一光致抗蚀剂层，以覆盖衬底上的栅电极，在第一光致抗蚀剂层上以增加的灵敏度形成第二光致抗蚀剂层，形成 在第二光致抗蚀剂层上具有降低的灵敏度的第三光致抗蚀剂层，在由第一至第三光致抗蚀剂层形成的光致抗蚀剂结构中形成开口，使得开口暴露栅电极，使得开口具有从 第一光致抗蚀剂层到第二光致抗蚀剂层。 此外，在包括开口的光致抗蚀剂结构上沉积低电阻金属层，使得金属层在栅电极上形成低电阻电极。

公开(公告)号：US6011281A

公开(公告)日：2000-01-04

申请号：US203335

申请日：1998-12-02

申请人： Mitsuji Nunokawa ,  Yutaka Sato

发明人： Mitsuji Nunokawa ,  Yutaka Sato

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/338 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/778 ,  H01L29/812 ,  H01L31/0328

CPC分类号： H01L29/7787 ,  H01L29/452 ,  H01L29/475

摘要： A semiconductor device includes an ohmic electrode and a Schottky electrode respectively carrying interconnection patterns with intervening adhesion layer and a diffusion barrier layer, wherein the Schottky electrode further includes a metal layer that prevents a reaction between the Schottky electrode and the diffusion barrier layer such that the metal layer is interposed between the top surface of the Schottky electrode and adhesion layer for increasing the distance between the diffusion barrier layer and the Schottky electrode.

摘要翻译： 半导体器件包括欧姆电极和肖特基电极，其分别承载具有中间粘附层和扩散阻挡层的互连图案，其中所述肖特基电极还包括防止肖特基电极和扩散阻挡层之间的反应的金属层，使得 金属层介于肖特基电极的顶表面和粘附层之间，用于增加扩散阻挡层和肖特基电极之间的距离。

公开(公告)号：US20110097886A1

公开(公告)日：2011-04-28

申请号：US12985742

申请日：2011-01-06

申请人： Kozo Makiyama ,  Naoya IKECHI ,  Takahiro Tan

发明人： Kozo Makiyama ,  Naoya IKECHI ,  Takahiro Tan

IPC分类号： H01L21/3205

CPC分类号： H01L21/0274 ,  H01L21/28114 ,  H01L21/28264 ,  H01L21/28587 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66871 ,  H01L29/78 ,  Y10S430/143 ,  Y10S438/949 ,  Y10S438/95 ,  Y10S438/951

摘要： A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

摘要翻译： 半导体器件具有：半导体衬底，具有电流流过的一对电流输入/输出区域; 形成在所述半导体基板上并具有栅电极开口的绝缘膜; 以及通过所述栅电极开口形成在所述半导体基板上的蘑菇栅极电极结构，所述蘑菇栅电极结构具有杆和形成在所述杆上的头部，所述杆在所述半导体衬底上沿着电流方向具有有限的尺寸，并且具有 向前锥形形状向上并沿着电流方向单调地增加尺寸，头部具有沿着电流方向逐步扩大的尺寸，并且杆在栅极电极开口中接触半导体衬底并且在至少一个位置附近骑绝缘膜 杆的相对端之一沿着当前方向。