公开(公告)号：US06743654B2

公开(公告)日：2004-06-01

申请号：US10014880

申请日：2001-12-11

Applicant: Salvatore Coffa ,  Luigi Occhipinti

Inventor： Salvatore Coffa ,  Luigi Occhipinti

IPC: H01L2100

CPC classification number: B81C1/00182 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C2201/0109 ,  B81C2201/0115 ,  G01L9/0042

Abstract: A method of making a monolithically integrated pressure sensor includes making a cavity in the semiconductor substrate. This may be formed by plasma etching the front side or the back side of the silicon wafer to cut a plurality of trenches or holes deep enough to extend for at least part of its thickness into a doped buried layer of opposite type of conductivity of the substrate and of the epitaxial layer grown over it. The method may also include electrochemically etching through such trenches, and the silicon of the buried layer with an electrolytic solution suitable for selectively etching the doped silicon of the opposite type of conductivity, thereby making the silicon of the buried layer porous. The method may also include oxidizing and leaching away the silicon so made porous.

Abstract translation: 制造单片集成压力传感器的方法包括在半导体衬底中形成空腔。 这可以通过等离子体蚀刻硅晶片的前侧或背面来形成，以切割多个深度足以将其厚度的至少一部分延伸到衬底的相反导电性的掺杂掩埋层中的沟槽或孔 以及在其上生长的外延层。 该方法还可以包括通过这样的沟槽进行电化学蚀刻，以及使用适合于选择性地蚀刻具有相反导电性的掺杂硅的电解液的掩埋层的硅，从而使掩埋层的硅多孔化。 该方法还可以包括氧化和浸出如此制成的多孔的硅。

公开(公告)号：US20040048430A1

公开(公告)日：2004-03-11

申请号：US10655839

申请日：2003-09-04

Inventor： Hubert Benzel ,  Hans Artmann ,  Frank Schaeffer

IPC: H01L021/8238

CPC classification number: B81C1/00182 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/0353 ,  B81C2201/0115 ,  B81C2201/0177 ,  G01L9/0042

Abstract: A semiconductor component and a method for a semiconductor substrate, in which a first section and a second section are provided, and in which the pore structure of the first section differs from the pore structure of the second section.

Abstract translation: 一种半导体元件和半导体衬底的方法，其中设置有第一部分和第二部分，并且其中第一部分的孔结构与第二部分的孔结构不同。

公开(公告)号：US20030127699A1

公开(公告)日：2003-07-10

申请号：US10328661

申请日：2002-12-23

Inventor： Hans Artmann ,  Thorsten Pannek

IPC: H01L021/00

CPC classification number: B81C1/0069 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0136 ,  B81C2201/0139

Abstract: In a method for producing a diaphragm sensor unit having a semiconductor material substrate, a flat diaphragm and an insulating well for thermal insulation below the diaphragm are generated, for the formation of sensor element structures for at least one sensor. The substrate, made of semiconductor material, in a specified region, which defines sensor element structures, receives a deliberately different doping from the surrounding semiconductor material, that porous semiconductor material is generated from semiconductor material sections between the regions distinguished by doping, and semiconductor material in the well region under semiconductor is rendered porous and under parts of the sensor element structure is removed and/or rendered porous.

Abstract translation: 在制造具有半导体材料基板的隔膜传感器单元的方法中，产生用于形成用于至少一个传感器的传感器元件结构的隔膜下方的平坦隔膜和隔热绝缘孔。 由限定传感器元件结构的特定区域中的由半导体材料制成的衬底接收与周围半导体材料的故意不同的掺杂，多孔半导体材料是由掺杂区域之间的半导体材料部分和半导体材料 在半导体中的阱区域被多孔化并且在传感器元件结构的部分被去除和/或变得多孔的情况下。

公开(公告)号：US06521313B1

公开(公告)日：2003-02-18

申请号：US10020353

申请日：2001-12-12

Applicant: Hans Artmann ,  Thorsten Pannek

Inventor： Hans Artmann ,  Thorsten Pannek

IPC: H01L2100

CPC classification number: B81B3/0081 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0136 ,  Y10T428/17

Abstract: In a method for producing a diaphragm sensor unit having a semiconductor material substrate, a flat diaphragm and an insulating well for thermal insulation below the diaphragm are generated, for the formation of sensor element structures for at least one sensor. The substrate, made of semiconductor material, in a specified region, which defines sensor element structures, receives a deliberately different doping from the surrounding semiconductor material, that porous semiconductor material is generated from semiconductor material sections between the regions distinguished by doping, and semiconductor material in the well region under semiconductor is rendered porous and under parts of the sensor element structure is removed and/or rendered porous.

公开(公告)号：US20020132101A1

公开(公告)日：2002-09-19

申请号：US10104749

申请日：2002-03-22

Applicant: The Penn State Research Foundation

Inventor： Stephen J. Fonash ,  Alikaan Kalkan ,  Sanghoon Bae

IPC: B32B003/26

CPC classification number: B81C1/0038 ,  B81C1/00047 ,  B81C2201/0115 ,  B81C2201/0139 ,  B81C2201/018 ,  C23C16/24 ,  C23C16/511 ,  G01N21/17 ,  G01N27/121 ,  G01N27/44717 ,  G01N30/6095 ,  H01J49/0418 ,  Y10T428/24174 ,  Y10T428/249953

Abstract: A novel porous film is disclosed comprising a network of silicon columns in a continuous void which may be fabricated using high density plasma deposition at low temperatures, i.e., less than about 250 null C. This silicon film is a two-dimensional nano-sized array of rodlike columns. This void-column morphology can be controlled with deposition conditions and the porosity can be varied up to 90%. The simultaneous use of low temperature deposition and etching in the plasma approach utilized, allows for the unique opportunity of obtaining columnar structure, a continuous void, and polycrystalline column composition at the same time. Unique devices may be fabricated using this porous continuous film by plasma deposition of this film on a glass, metal foil, insulator or plastic substrates.

Abstract translation: 公开了一种新颖的多孔膜，其包括在连续空隙中的硅柱网络，其可以在低温下（即小于约250℃）下使用高密度等离子体沉积来制造。该硅膜是二维纳米尺寸阵列 的棒状柱。 这种空隙柱形态可以用沉积条件控制，并且孔隙率可以变化高达90％。 在所采用的等离子体方法中同时使用低温沉积和蚀刻允许在同时获得柱状结构，连续空隙和多晶柱组成的独特机会。 可以使用这种多孔连续膜通过将该膜等离子体沉积在玻璃，金属箔，绝缘体或塑料基底上来制造独特的器件。

公开(公告)号：US20020020053A1

公开(公告)日：2002-02-21

申请号：US09836449

申请日：2001-04-17

Inventor： Stephen J. Fonash ,  Wook Jun Nam ,  Youngchul Lee ,  Kyuhwan Chang ,  Daniel J. Hayes ,  A. Kaan Kalkan ,  Sanghoon Bae

IPC: H01M006/02 ,  H01L021/00 ,  H01L021/84 ,  G03F007/26 ,  H05K003/00 ,  H01B013/00 ,  B32B031/12 ,  C23F001/02 ,  C23C014/34 ,  C03C015/00 ,  H05K003/46

CPC classification number: B81C1/0038 ,  B81C1/00119 ,  B81C1/00476 ,  B81C2201/0115 ,  G01N21/17 ,  G01N27/44717 ,  Y10T29/49108

Abstract: This invention uses large surface to volume ratio materials for separation, release layer, and sacrificial material applications. The invention outlines the material concept, application designs, and fabrication methodologies. The invention is demonstrated using deposited column/void network materials as examples of large surface to volume ratio materials. In a number of the specific applications discussed, it is shown that it is advantageous to create structures on a laminate on a mother substrate and then, using the separation layer material approach, to separate this laminate from the mother substrate using the present separation scheme. It is also shown that the present materials have excellent release layer utility. In a number of applications it is also shown how the approach can be used to uniquely form cavities, channels, air-gaps, and related structures in or on various substrates. Further, it is demonstrated that it also can be possible and advantageous to combine the schemes for cavity formation with the scheme for laminate separation.

Abstract translation: 本发明使用大的表面体积比的材料用于分离，剥离层和牺牲材料应用。 本发明概述了材料概念，应用设计和制造方法。 本发明使用沉积柱/空隙网络材料作为大表面积与体积比的材料的实例进行了说明。 在讨论的许多具体应用中，显示了在母基板上的层压体上产生结构，然后使用分离层材料方法，使用本分离方案将该层压体与母基板分离是有利的。 还显示出本发明材料具有优异的脱模层效用。 在许多应用中，还显示了该方法如何用于在各种基底中或其上独特地形成腔，通道，气隙和相关结构。 此外，证明了将空腔形成方案与层压分离方案组合也是有可能和有利的。

公开(公告)号：US09771259B2

公开(公告)日：2017-09-26

申请号：US14932814

申请日：2015-11-04

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu

IPC: B81C1/00 ,  H01L21/683 ,  H01L23/00

CPC classification number: B81C1/00325 ,  B81B2207/092 ,  B81B2207/097 ,  B81C1/00301 ,  B81C2201/0115 ,  B81C2203/0118 ,  H01L21/6835 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/93 ,  H01L2221/68304 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2221/68386 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/11009 ,  H01L2224/11019 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/93 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15788 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2924/00

Abstract: The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.

公开(公告)号：US09527729B2

公开(公告)日：2016-12-27

申请号：US14182659

申请日：2014-02-18

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Eric Ollier

IPC: B81C1/00

CPC classification number: B81C1/00515 ,  B81C1/00206 ,  B81C1/00412 ,  B81C1/00626 ,  B81C2201/0114 ,  B81C2201/0115 ,  B81C2201/038

Abstract: Process for fabrication of a micromechanical and/or nanomechanical structure comprising the following steps, starting from an element comprising a support substrate and a sacrificial layer: a) formation of a first layer, at least part of which is porous, b) formation on the first layer of a layer made of one (or several) materials providing the mechanical properties of the structure, called the intermediate layer, c) formation on the intermediate layer of a second layer, at least part of which is porous, d) formation of said structure in the stack composed of the first layer, the intermediate layer and the second layer, e) release of said structure by at least partial removal of the sacrificial layer.

Abstract translation: 该方法包括形成第一层即硅层（6），其部分是多孔的，并且在第一层上形成层间（16）以确保结构的机械性能。 第二层形成在层间，其中第二层的一部分是多孔的。 该结构形成在第一层，层间和第二层的堆叠中，其中第一和第二层由多孔硅锗制成，并且层间由非多孔硅锗制成。 通过牺牲层（4）的部分抽出来释放结构。

公开(公告)号：US20160200568A1

公开(公告)日：2016-07-14

申请号：US14914215

申请日：2013-08-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, LP

Inventor： Patrick Wayne Sadik ,  Roger A. McKay

IPC: B81C1/00 ,  B41J2/16

CPC classification number: B81C1/00063 ,  B41J2/162 ,  B41J2/1626 ,  B81B2201/052 ,  B81C2201/0115 ,  B81C2201/0133 ,  B81C2201/0181

Abstract: An example provides a method including sputtering a metal catalyst onto a substrate, exposing the substrate to a solution that reacts with the metal catalyst to form a plurality of pores in the substrate, and etching the substrate to remove the plurality of pores to form a recess in the substrate.

公开(公告)号：US20160137493A1

公开(公告)日：2016-05-19

申请号：US14207752

申请日：2014-03-13

Applicant: Robert Bosch GmbH

Inventor： Ashwin Samarao ,  Gary O'Brien ,  Ando Feyh ,  Gary Yama ,  Andrew Graham ,  Bongsang Kim ,  Fabian Purkl

IPC: B81C1/00

CPC classification number: B81C1/00285 ,  B81C2201/0115 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/035 ,  H01L21/3223 ,  H01L21/3225 ,  H01L23/28

Abstract: A microelectromechanical system (MEMS) device includes a high density getter. The high density getter includes a silicon surface area formed by porosification or by the formation of trenches within a sealed cavity of the device. The silicon surface area includes a deposition of titanium or other gettering material to reduce the amount of gas present in the sealed chamber such that a low pressure chamber is formed. The high density getter is used in bolometers and gyroscopes but is not limited to those devices.

Abstract translation: 微机电系统（MEMS）装置包括高密度吸气剂。 高密度吸气剂包括通过孔化形成的硅表面积或通过在该装置的密封腔内形成沟槽。 硅表面积包括钛或其它吸气材料的沉积物，以减少密封室中存在的气体的量，从而形成低压室。 高密度吸气剂用于测辐射仪和陀螺仪，但不限于这些设备。