公开(公告)号：US20170018303A1

公开(公告)日：2017-01-19

申请号：US15281312

申请日：2016-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hao-I YANG ,  Chia-En HUANG ,  Cheng Hung LEE ,  Geng-Cing LIN ,  Jung-Ping YANG

IPC: G11C11/419 ,  G11C7/18 ,  H01L27/11 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/06 ,  G11C8/18 ,  H01L27/1104 ,  H01L27/1116

Abstract: A circuit includes: a first data line; a second data line; a write driver including first and second transistors; a first switch connected in series with the first transistor to form a first series-connected pair; a second switch in series with the second transistor to form a second series-connected pair; and a level shifter which includes the first and second transistors. The first series-connected pair is coupled between a first voltage node and the first data line. The second series-connected pair is coupled between the first voltage node and the second data line. Gate terminals of the first and second transistors are correspondingly cross-coupled with the second and first data lines.

Abstract translation: 电路包括：第一数据线; 第二条数据线 包括第一和第二晶体管的写入驱动器; 与所述第一晶体管串联连接的第一开关，以形成第一串联对; 与所述第二晶体管串联的第二开关，以形成第二串联连接对; 以及包括第一和第二晶体管的电平移位器。 第一串联对耦合在第一电压节点和第一数据线之间。 第二串联对耦合在第一电压节点和第二数据线之间。 第一和第二晶体管的栅极端子与第二和第一数据线相应地交叉耦合。

公开(公告)号：US09542997B2

公开(公告)日：2017-01-10

申请号：US14877278

申请日：2015-10-07

Applicant: Broadcom Corporation

Inventor： Ali Anvar ,  Gil I. Winograd ,  Esin Terzioglu

IPC: G11C7/06 ,  G11C11/419 ,  G06F13/40 ,  G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/412 ,  G11C11/413 ,  G11C29/00 ,  G11C7/12 ,  G11C11/41

CPC classification number: G11C11/419 ,  G06F13/4086 ,  G11C5/025 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global data latch operable to receive a sensed data state from the local sense amplifier.

Abstract translation: 系统包括存储器块。 存储块包括可操作以控制存储器块的存储器操作的本地控制电路。 本地控制电路包括本地读出放大器。 该系统还包括与存储块分离的全局存储器控制电路，并且全局存储器控制电路可操作以与本地控制电路通信。 全局存储器控制电路包括全局数据锁​​存器，用于从本地读出放大器接收感测的数据状态。

公开(公告)号：US09542980B1

公开(公告)日：2017-01-10

申请号：US15083303

申请日：2016-03-29

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Adam Saleh El-Mansouri ,  Adrian Jay Drexler ,  Ryan Martin Hofstetter

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C7/06 ,  G11C7/18

Abstract: A memory array structure includes: a plurality of array sections and a plurality of mini-gaps, wherein each mini-gap is disposed between two array sections of the plurality of array sections. Each mini-gap includes: a local write device, for providing a data signal in response to a write enable signal and a write data signal, the data signal for performing a write operation on a memory cell of an array section; and a local sensor, for outputting a data signal in response to an activation command and a read enable signal. The memory array further includes a control logic for providing the write enable and read enable signals, and at least one main sense amplifier, for providing the write data signal to the local write device, receiving the data signal from the local sensor, and amplifying the received data signal for providing a read data signal to output data lines.

Abstract translation: 存储器阵列结构包括：多个阵列部分和多个微型间隙，其中每个微小间隙设置在多个阵列部分的两个阵列部分之间。 每个小间隙包括：本地写装置，用于响应于写使能信号和写数据信号提供数据信号，用于对阵列部分的存储单元执行写操作的数据信号; 以及本地传感器，用于响应于激活命令和读使能信号而输出数据信号。 存储器阵列还包括用于提供写入使能和读取使能信号的控制逻辑，以及至少一个主读出放大器，用于将写入数据信号提供给本地写入器件，从本地传感器接收数据信号，以及放大 接收的数据信号用于提供读取数据信号以输出数据线。

公开(公告)号：US09530469B2

公开(公告)日：2016-12-27

申请号：US13843306

申请日：2013-03-15

Applicant: Sony Corporation

Inventor： Makoto Kitagawa ,  Tomohito Tsushima ,  Wataru Otsuka ,  Takafumi Kunihiro

IPC: G11C13/00 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C7/12 ,  G11C7/18

Abstract: An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line.

Abstract translation: 一种集成电路系统及其制造方法，包括：集成电路管芯; 集成电路管芯中的非易失性存储单元，具有用于读取非易失性存储单元的数据状态的位线; 和集成电路管芯中的电压钳，电压钳具有连接到位线的半导体开关，用于减少位线上的电压偏移。

公开(公告)号：US09524920B2

公开(公告)日：2016-12-20

申请号：US14077252

申请日：2013-11-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Lin ,  Kao-Cheng Lin ,  Li-Wen Wang ,  Yen-Huei Chen

IPC: H01L23/48 ,  H01L25/065 ,  G11C5/06 ,  G11C7/18 ,  H01L27/06

CPC classification number: H01L23/481 ,  G11C5/063 ,  G11C7/18 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

Abstract translation: 一种三维导线的装置和方法，包括第一层中的第一存储器列段，第二层中的第二存储器列段，以及将第一存储器列段连接到第二存储器列段的导线。 在一些实施例中，导线被布置在存储器列的第一侧上的第一层中，并且位于存储器列的第二侧上的第二层中。

公开(公告)号：US09520199B2

公开(公告)日：2016-12-13

申请号：US14692927

申请日：2015-04-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuo-Pin Chang

IPC: G11C16/04 ,  G11C16/28 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C7/18 ,  G11C16/0433 ,  G11C16/28 ,  G11C16/3427 ,  H01L27/11582

Abstract: A memory device includes: a plurality of conductive stacked structures including at least a string select line, a plurality of word lines and at least a ground select line; a plurality of memory cells formed in the conductive stacked structures; a plurality of bit lines, formed on the conductive stacked structures; and at least an odd common source line and at least an even common source line, formed on the conductive stacked structures. The odd common source line is coupled to a plurality of odd bit lines of the bit lines. The even common source line is coupled to a plurality of even bit lines of the bit lines.

Abstract translation: 存储器件包括：至少包括串选择线，多个字线和至少一地选线的多个导电堆叠结构; 形成在所述导电堆叠结构中的多个存储单元; 多个位线，形成在导电堆叠结构上; 以及形成在导电堆叠结构上的至少一个奇数公共源极线和至少一个偶数公共源极线。 奇数公共源极线耦合到位线的多个奇数位线。 偶数公共源极线耦合到位线的多个偶数位线。

公开(公告)号：US20160336050A1

公开(公告)日：2016-11-17

申请号：US14709017

申请日：2015-05-11

Applicant: Wisconsin Alumni Research Foundation

Inventor： Jing Li

IPC: G11C7/10 ,  G11C5/06 ,  G06F13/40

CPC classification number: G11C7/10 ,  G06F13/4022 ,  G11C5/025 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/14 ,  G11C11/005 ,  G11C13/0002 ,  G11C13/0021 ,  G11C15/046 ,  G11C2207/005 ,  G11C2213/77

Abstract: A computer architecture employs multiple intercommunicating tiles each holding an array of memory elements. Programmable decoding circuitry allows these memory elements to be used as local memories (including content addressable memories or random access memories), logic elements or interconnect elements. The ability to dynamically change the function of any of these tiles allows tight integration of memory and logic tailored to particular calculation problems reducing costs in data transfer.

Abstract translation: 计算机体系结构采用多个互通瓦片，每个保持一组存储器元件。 可编程解码电路允许这些存储器元件用作本地存储器（包括内容寻址存储器或随机存取存储器），逻辑元件或互连元件。 动态改变任何这些瓦片功能的能力允许紧密集成存储器和逻辑，以适应特定的计算问题，从而降低数据传输中的成本。

公开(公告)号：US09484084B2

公开(公告)日：2016-11-01

申请号：US14920209

申请日：2015-10-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hao-I Yang ,  Chia-En Huang ,  Cheng Hung Lee ,  Geng-Cing Lin ,  Jung-Ping Yang

IPC: G11C7/00 ,  G11C11/419 ,  G11C7/10 ,  G11C8/06 ,  G11C8/18 ,  G11C7/18 ,  G11C7/22

CPC classification number: G11C11/419 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/06 ,  G11C8/18 ,  H01L27/1104 ,  H01L27/1116

Abstract: A circuit includes a first data line, a second data line, a first pulling device, a second pulling device, a third pulling device, and a fourth pulling device. The first pulling device is configured to be activated or deactivated responsive to a first control signal; and is configured to pull a first signal at the first data line toward a voltage level of a first voltage based on a second signal at the second data line when the first pulling device is activated. The second pulling device is configured to be activated or deactivated responsive to a second control signal; and is configured to pull the second signal at the second data line toward the voltage level of the first voltage based on the first signal at the first data line when the second pulling device is activated.

Abstract translation: 电路包括第一数据线，第二数据线，第一牵引装置，第二牵引装置，第三牵引装置和第四牵引装置。 第一牵引装置被配置为响应于第一控制信号被激活或停用; 并且被配置为当第一牵引装置被激活时，基于第二数据线处的第二信号将第一数据线处的第一信号拉向第一电压的电压电平。 第二牵引装置被配置为响应于第二控制信号被激活或停用; 并且被配置为当第二拉动装置被启动时，基于第一数据线处的第一信号将第二数据线处的第二信号拉向第一电压的电压电平。

公开(公告)号：US20160307836A1

公开(公告)日：2016-10-20

申请号：US14687015

申请日：2015-04-15

Applicant: Macronix International Co., Ltd.

Inventor： Ya Jung TSai ,  Lan Ting Huang ,  Kuo NaiPing ,  Chun-Lien Su

IPC: H01L23/528 ,  H01L29/78 ,  H01L29/08 ,  H01L27/105

CPC classification number: H01L29/0847 ,  G11C7/18 ,  H01L27/0207

Abstract: A semiconductor memory device is provided including a plurality of diffusion region pairs comprising first and second diffusion regions, wherein each of the diffusion regions comprise source and drain regions of a bit line transistor pair comprising a first bit line transistor and a second bit line transistor and a plurality of bit line transistor gate pairs in contact with the respective diffusion region pairs, wherein the first bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of a first bit line transistor of the first diffusion region and the first bit lite transistor of the second diffusion region, wherein a second bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of the second bit line transistor of the first diffusion region and the second bit line transistor of the second diffusion layer.

Abstract translation: 提供一种半导体存储器件，其包括多个扩散区域对，其包括第一和第二扩散区域，其中每个扩散区域包括包含第一位线晶体管和第二位线晶体管的位线晶体管对的源区和漏区， 与相应的扩散区域对接触的多个位线晶体管栅极对，其中位线晶体管栅极对的第一位线晶体管栅极包括第一扩散区域的第一位线晶体管的栅极部分和第一位 位线晶体管栅极对的第二位线晶体管栅极包括第一扩散区域的第二位线晶体管的栅极部分和第二扩散层的第二位线晶体管。

公开(公告)号：US09465905B1

公开(公告)日：2016-10-11

申请号：US14870112

申请日：2015-09-30

Applicant: International Business Machines Corporation

Inventor： Lior Arie ,  Lidar Herooti ,  Noam Jungmann ,  Elazar Kachir ,  Hezi Shalom ,  Israel A. Wagner

IPC: G11C11/00 ,  G06F17/50 ,  G11C16/10 ,  G11C7/18 ,  G11C11/413 ,  G11C16/08 ,  G11C11/412 ,  G11C11/419 ,  G11C16/04

CPC classification number: G11C11/419 ,  G06F17/5077 ,  G06F17/5081 ,  G11C7/18 ,  G11C11/412 ,  G11C11/413 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: A method in a computer-aided design system for generating a functional design model of a static random access memory is described herein. The method comprises generating a functional representation of a first local evaluation logic coupled to a first set of consecutive global bit lines (GBLs) and a first set of local bit lines (LBLs), the first local evaluation logic comprising a plurality of devices. The method further comprises generating a functional representation of a second local evaluation logic communicatively coupled to the first local evaluation logic via the devices; the second local evaluation logic is coupled to a second set of consecutive GBLs and a second set of LBLs. In addition, the second set of consecutive GBLs consecutive to the first set of consecutive GBLs, the first and second evaluation logics to generate signals from the LBLs such that one GBL is to be active at any point in a read or write cycle and the other GBLs are not concurrently active.

Abstract translation: 这里描述了用于生成静态随机存取存储器的功能设计模型的计算机辅助设计系统中的方法。 该方法包括生成耦合到第一组连续全局位线（GBL）和第一组局部位线（LBL）的第一局部评估逻辑的功能表示，所述第一局部评估逻辑包括多个设备。 该方法还包括通过设备生成通信地耦合到第一本地评估逻辑的第二本地评估逻辑的功能表示; 第二本地评估逻辑耦合到第二组连续GBL和第二组LBL。 另外，第二组连续的GBL连续到第一组连续GBL，第一和第二评估逻辑从LBL生成信号，使得一个GBL将在读或写周期中的任何一点处于活动状态 GBL不同时活动。