公开(公告)号：US20130273691A1

公开(公告)日：2013-10-17

申请号：US13445550

申请日：2012-04-12

Applicant: Daniel PASCUAL ,  Jeremiah HEBDING ,  Megha RAO ,  Colin McDONOUGH ,  Douglas Duane COOLBAUGH ,  Joseph PICCIRILLO, JR. ,  Michael LIEHR

Inventor： Daniel PASCUAL ,  Jeremiah HEBDING ,  Megha RAO ,  Colin McDONOUGH ,  Douglas Duane COOLBAUGH ,  Joseph PICCIRILLO, JR. ,  Michael LIEHR

IPC: H01L21/50 ,  B23K37/04 ,  H01L21/762

CPC classification number: B23K1/0016 ,  B23K1/20 ,  B23K3/087 ,  B23K2101/42 ,  H01L21/6835 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L24/97 ,  H01L2221/68313 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/08146 ,  H01L2224/75315 ,  H01L2224/7532 ,  H01L2224/7598 ,  H01L2224/80004 ,  H01L2224/80203 ,  H01L2224/80205 ,  H01L2224/80357 ,  H01L2224/80801 ,  H01L2224/80895 ,  H01L2224/80986 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81898 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/1461 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/80 ,  H01L2924/00

Abstract: A method is provided for bonding a die to a base technology wafer and includes: providing a device wafer having a front, back, at least one side, and at least one TSV, wherein the back contains a substrate material; providing a carrier wafer having a front, back, and at least one side; bonding the wafers using an adhesive; removing the substrate material and wet etching, from the device wafer's back side, to expose at least one metallization scheme feature; processing the device wafer's back side to create at least one backside redistribution layer; removing the device wafer from the carrier wafer; dicing the device wafer into individual die; providing a base technology wafer; coating the front of the base technology wafer with a sacrificial adhesive; placing the front of the individual die onto the front of the base technology wafer; and bonding the individual die to the base technology wafer.

Abstract translation: 提供了一种用于将管芯结合到基底技术晶片的方法，包括：提供具有前部，后部，至少一个侧面和至少一个TSV的器件晶片，其中所述背面包含衬底材料; 提供具有前，后和至少一侧的载体晶片; 使用粘合剂粘合晶片; 从器件晶片的背面去除衬底材料和湿蚀刻，以暴露至少一个金属化方案特征; 处理器件晶片的背面以创建至少一个背面再分布层; 从载体晶片去除器件晶片; 将器件晶片切割成单个管芯; 提供基础技术晶圆; 用牺牲粘合剂涂覆基底技术晶片的前部; 将单个模具的前部放置在基底技术晶片的前部; 并将单个管芯结合到基底技术晶片。

公开(公告)号：US08501537B2

公开(公告)日：2013-08-06

申请号：US13076840

申请日：2011-03-31

Applicant: Mariam Sadaka ,  Ionut Radu ,  Didier Landru ,  Lea Di Cioccio

Inventor： Mariam Sadaka ,  Ionut Radu ,  Didier Landru ,  Lea Di Cioccio

IPC: H01L21/00 ,  H01L21/30 ,  H01L21/46

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0384 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/05546 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08121 ,  H01L2224/08146 ,  H01L2224/8001 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81948 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Methods of bonding together semiconductor structures include annealing a first metal feature on a first semiconductor structure, bonding the first metal feature to a second metal feature of a second semiconductor structure to form a bonded metal structure that comprises the first metal feature and the second metal feature, and annealing the bonded metal structure. Annealing the first metal feature may comprise subjecting the first metal feature to a pre-bonding thermal budget, and annealing the bonded metal structure may comprise subjecting the bonded metal structure to a post-bonding thermal budget that is less than the pre-bonding thermal budget. Bonded semiconductor structures are fabricated using such methods.

Abstract translation: 将半导体结构结合在一起的方法包括退火第一半导体结构上的第一金属特征，将第一金属特征结合到第二半导体结构的第二金属特征，以形成包含第一金属特征和第二金属特征 ，并对结合的金属结构进行退火。 退火第一金属特征可以包括使第一金属特征经受预结合热预算，并且对接合的金属结构进行退火可以包括使结合的金属结构经受低于预粘合热预算的后粘合热预算 。 使用这种方法制造粘合的半导体结构。

公开(公告)号：US08475612B2

公开(公告)日：2013-07-02

申请号：US12897491

申请日：2010-10-04

Applicant: Gweltaz Gaudin

Inventor： Gweltaz Gaudin

IPC: B32B41/00 ,  B32B37/10

CPC classification number: H01L21/185 ,  B32B37/144 ,  B32B37/18 ,  B32B38/1808 ,  B32B38/1866 ,  B32B41/00 ,  B32B2041/04 ,  B32B2307/202 ,  B32B2309/72 ,  B32B2457/14 ,  H01L21/187 ,  H01L24/75 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/75702 ,  H01L2224/75703 ,  H01L2224/75756 ,  H01L2224/75901 ,  H01L2224/80006 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/94 ,  H01L2924/3511 ,  Y10T156/10 ,  Y10T156/1089 ,  Y10T156/1092 ,  H01L2224/80

Abstract: A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.

Abstract translation: 一种用于通过分子粘合将第一晶片接合在第二晶片上的方法，其中晶片在它们之间具有初始的径向不对准。 该方法包括使两个晶片接触，以便在两个晶片之间启动键合波的传播，同时在接触步骤期间将两个晶片中的至少一个施加预定的接合曲率作为初始径向失准的函数 。

公开(公告)号：US20130040423A1

公开(公告)日：2013-02-14

申请号：US13206602

申请日：2011-08-10

Applicant: Chih-Hang Tung ,  Chun Hui Yu ,  Chen-Hua Yu ,  Da-Yuan Shih

Inventor： Chih-Hang Tung ,  Chun Hui Yu ,  Chen-Hua Yu ,  Da-Yuan Shih

IPC: H01L21/56 ,  H01L21/82

CPC classification number: H01L25/50 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02311 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/08146 ,  H01L2224/12105 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/03

Abstract: A method of multi-chip wafer level packaging comprises forming a reconfigured wafer using a plurality of photo-sensitive material layers. A plurality of semiconductor chips and wafers are embedded in the photo-sensitive material layers. Furthermore, a variety of through assembly vias are formed in the photo-sensitive material layers. Each semiconductor chip embedded in the photo-sensitive material layers is connected to input/output pads through connection paths formed by the through assembly vias.

Abstract translation: 多芯片晶片级封装的方法包括使用多个感光材料层形成重新配置的晶片。 多个半导体芯片和晶片被嵌入到感光材料层中。 此外，在感光材料层中形成各种贯穿组装通孔。 嵌入在感光材料层中的每个半导体芯片通过由通孔组装通孔形成的连接路径连接到输入/输出焊盘。

公开(公告)号：US20120006463A1

公开(公告)日：2012-01-12

申请号：US12897491

申请日：2010-10-04

Applicant: Gweltaz Gaudin

Inventor： Gweltaz Gaudin

IPC: B32B37/02

CPC classification number: H01L21/185 ,  B32B37/144 ,  B32B37/18 ,  B32B38/1808 ,  B32B38/1866 ,  B32B41/00 ,  B32B2041/04 ,  B32B2307/202 ,  B32B2309/72 ,  B32B2457/14 ,  H01L21/187 ,  H01L24/75 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/75702 ,  H01L2224/75703 ,  H01L2224/75756 ,  H01L2224/75901 ,  H01L2224/80006 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/94 ,  H01L2924/3511 ,  Y10T156/10 ,  Y10T156/1089 ,  Y10T156/1092 ,  H01L2224/80

Abstract: A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.

Abstract translation: 一种用于通过分子粘合将第一晶片接合在第二晶片上的方法，其中晶片在它们之间具有初始的径向不对准。 该方法包括使两个晶片接触，以便在两个晶片之间启动键合波的传播，同时在接触步骤期间将两个晶片中的至少一个施加预定的接合曲率作为初始径向失准的函数 。

公开(公告)号：US20240363565A1

公开(公告)日：2024-10-31

申请号：US18768080

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jen-Yuan CHANG

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065

CPC classification number: H01L24/06 ,  H01L22/32 ,  H01L24/03 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/031 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06505 ,  H01L2224/06515 ,  H01L2224/08146 ,  H01L2224/80001

Abstract: A semiconductor package structure includes a first die, a second die disposed on the first die, and a bonding pad structure. The first die includes a semiconductor substrate, an interconnect structure disposed on the first semiconductor substrate, a passivation layer disposed on the interconnect structure, and a test pad disposed on the passivation layer. The test pad includes a contact region that extends through the passivation layer and electrically contacts the interconnect structure, and a bonding recess that overlaps with the contact region in a vertical direction perpendicular to a plane of the first semiconductor substrate. The bonding pad structure electrically connects the first die and the second die and directly contacts at least a portion of the bonding recess.

公开(公告)号：US20240355780A1

公开(公告)日：2024-10-24

申请号：US18387707

申请日：2023-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhyeon KIM ,  Chajea JO

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L2224/08146 ,  H01L2924/181

Abstract: Semiconductor packages and fabrication methods thereof are provided. A semiconductor package includes first and second structures. The first structure includes: a first semiconductor substrate that has an active surface on which a first semiconductor device is configured to be provided, and an inactive surface opposite to the active surface; a first through via that vertically penetrates the first semiconductor substrate and protrudes from the inactive surface of the first semiconductor substrate; a first protection layer that covers the inactive surface of the first semiconductor substrate and buries the first through via; and a first pad that penetrates at least a portion of the first protection layer and is coupled to the first through via. The second structure includes a second pad, the first structure and the second structure are bonded to each other, and the first pad and the second pad are in contact with each other.

公开(公告)号：US20240332255A1

公开(公告)日：2024-10-03

申请号：US18742838

申请日：2024-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  JIHOON KIM ,  JiHwan SUH ,  SO YOUN LEE ,  JIHWAN HWANG ,  TAEHUN KIM ,  JI-SEOK HONG

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

公开(公告)号：US20240332229A1

公开(公告)日：2024-10-03

申请号：US18619071

申请日：2024-03-27

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Tzu Ching Hung ,  Kyle K. Kirby ,  Julia VanWinkle ,  Kyle B. Campbell ,  Bret K. Street

IPC: H01L23/00 ,  H01L21/66

CPC classification number: H01L24/06 ,  H01L22/32 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/06517 ,  H01L2224/08146

Abstract: A semiconductor device is provided. The semiconductor device can have a front side at which circuitry is disposed. The circuitry can include a pad and a plurality of lines. A first layer of dielectric material can be disposed at the front side at least partially over the pad and the plurality of lines. A second layer of dielectric material can be disposed at the front side at least partially over the first layer of dielectric material. A dual damascene pad can extend through the first layer of dielectric material and the second layer of dielectric material to the pad. A dummy pad can be disposed in the second layer of dielectric material above the plurality of lines and spaced from the dual damascene pad. In doing so, a reliable semiconductor device can be implemented.

公开(公告)号：US20240321857A1

公开(公告)日：2024-09-26

申请号：US18736766

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhyeon Kim ,  Hyoeun Kim ,  Sunkyoung Seo

IPC: H01L25/00 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/03 ,  H01L24/80 ,  H01L24/94 ,  H01L24/97 ,  H01L24/08 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/08146 ,  H01L2224/80001 ,  H01L2225/06541

Abstract: A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.