公开(公告)号：US20150137320A1

公开(公告)日：2015-05-21

申请号：US14538046

申请日：2014-11-11

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： JUNG-HWAN KIM ,  HUN-HYEOUNG LEAM ,  TAE-HYUN KIM ,  SEOK-WOO NAM ,  HYUN NAMKOONG ,  YONG-SEOK KIM ,  TEA-KWANG YU

IPC分类号： H01L29/06 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

摘要： A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

摘要翻译： 半导体器件包括限定形成在半导体衬底中的有源区的隔离层。 在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。 执行第一舍入处理以围绕活动区域的边缘部分。 在隔离层上进行第二凹陷处理。 执行第二舍入处理以围绕活动区域的边缘部分。

公开(公告)号：US20150115342A1

公开(公告)日：2015-04-30

申请号：US14517657

申请日：2014-10-17

申请人： Renesas Electronics Corporation

发明人： Yoshinori KAYA ,  Yasushi NAKAHARA ,  Azuma ARAYA ,  Ryo KANDA ,  Tomonobu KURIHARA ,  Tetsu TODA

IPC分类号： H01L27/06 ,  H01L29/06

CPC分类号： H02M1/088 ,  H01L27/0285 ,  H01L27/0292 ,  H01L27/0296 ,  H01L27/0629 ,  H01L27/0922 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1079 ,  H01L29/405 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7838 ,  H03K2017/6875 ,  H03K2217/0081

摘要： Provided is a semiconductor device including a substrate of a first conductivity type, a first circuit region, a separation region, a second circuit region, and a rectifying element. The rectifying element has a second conductivity type layer, a first high concentration second conductivity type region, a second high concentration second conductivity type region, an element isolation film, a first insulation layer, and a first conductive film. A first contact is coupled to the first high concentration second conductivity type region, and a second contact is coupled to the second high concentration second conductivity type region. A third contact is coupled to the first conductive film. The first contact, the second contact and the third contact are separated from each other.

摘要翻译： 提供了包括第一导电类型的衬底，第一电路区域，分离区域，第二电路区域和整流元件的半导体器件。 整流元件具有第二导电类型层，第一高浓度第二导电类型区域，第二高浓度第二导电类型区域，元件隔离膜，第一绝缘层和第一导电膜。 第一触点耦合到第一高浓度第二导电类型区域，第二触点耦合到第二高浓度第二导电类型区域。 第三触点耦合到第一导电膜。 第一触点，第二触点和第三触点彼此分离。

公开(公告)号：US08994026B2

公开(公告)日：2015-03-31

申请号：US13774205

申请日：2013-02-22

申请人： International Business Machines Corporation

发明人： Steven H. Voldman

IPC分类号： H01L27/108 ,  H01L27/092 ,  H01L29/66 ,  H01L29/792 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L27/092 ,  H01L21/823892 ,  H01L27/0921 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/66833 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7923

摘要： Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.

摘要翻译： 制造结构的设计结构，结构和方法，为混合电压集成电路提供闭锁抑制。 该结构包括嵌入在P晶片中并且在逆向N阱下面提供到非隔离CMOS逻辑的扩散N型Tub结构。

公开(公告)号：US20150041764A1

公开(公告)日：2015-02-12

申请号：US14521910

申请日：2014-10-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sang-moon LEE ,  Young-jin CHO

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/205 ,  H01L29/15

CPC分类号： H01L29/78 ,  H01L29/0657 ,  H01L29/1075 ,  H01L29/1079 ,  H01L29/15 ,  H01L29/205 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/7783

摘要： Semiconductor devices including a substrate (e.g., silicon substrate), a multi-layer structure disposed on a portion of the substrate, and at least one electrode disposed on the multi-layer structure and methods of manufacturing the same are provided. The multi-layer structure may include an active layer containing a Group III-V material and a current blocking layer disposed between the substrate and the active layer. The semiconductor device may further include a buffer layer disposed between the substrate and the active layer. In a case that the substrate is a p-type, the buffer layer may be an n-type material layer and the current blocking layer may be a p-type material layer. The current blocking layer may contain a Group III-V material. A mask layer having an opening may be disposed on the substrate so that the multi-layer structure may be disposed on the portion of the substrate exposed by the opening.

摘要翻译： 提供了包括衬底（例如，硅衬底），设置在衬底的一部分上的多层结构以及设置在多层结构上的至少一个电极的半导体器件及其制造方法。 多层结构可以包括含有III-V族材料的有源层和设置在衬底和有源层之间的电流阻挡层。 半导体器件还可以包括设置在衬底和有源层之间的缓冲层。 在基板是p型的情况下，缓冲层可以是n型材料层，电流阻挡层可以是p型材料层。 电流阻挡层可以含有III-V族材料。 具有开口的掩模层可以设置在基板上，使得多层结构可以设置在由开口暴露的基板的部分上。

公开(公告)号：US20140367700A1

公开(公告)日：2014-12-18

申请号：US13920621

申请日：2013-06-18

申请人： Infineon Technologies Austria AG

发明人： Gerhard Prechtl ,  Clemens Ostermaier ,  Oliver Häberlen

IPC分类号： H01L27/06 ,  H01L29/20 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/872 ,  H01L29/778

CPC分类号： H01L27/0629 ,  H01L21/8234 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/1075 ,  H01L29/1079 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/872 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2924/00014

摘要： An embodiment of a cascaded diode having a breakdown voltage exceeding 300V includes an HEMT and a Si Schottky diode. The HEMT includes a gate, a drain, a source, and a two-dimensional electron gas channel region connecting the source and the drain and controlled by the gate. The HEMT has a breakdown voltage exceeding 300V. The Si Schottky diode is monolithically integrated with the HEMT. The Si Schottky diode includes a cathode connected to the source of the HEMT and an anode connected to the gate of the HEMT. The Si Schottky diode has a breakdown voltage less than 300V and a forward voltage less than or equal to 0.4V. The anode of the Si Schottky diode forms the anode of the cascaded diode and the drain of the HEMT forms the cathode of the cascaded diode.

摘要翻译： 击穿电压超过300V的级联二极管的实施例包括HEMT和Si肖特基二极管。 HEMT包括连接源极和漏极并由栅极控制的栅极，漏极，源极和二维电子气体通道区域。 HEMT的击穿电压超过300V。 Si肖特基二极管与HEMT整体集成。 Si肖特基二极管包括连接到HEMT的源极的阴极和连接到HEMT的栅极的阳极。 Si肖特基二极管的击穿电压小于300V，正向电压小于或等于0.4V。 Si肖特基二极管的阳极形成级联二极管的阳极，HEMT的漏极形成级联二极管的阴极。

公开(公告)号：US20140346576A1

公开(公告)日：2014-11-27

申请号：US14455102

申请日：2014-08-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Yuan Lu

IPC分类号： H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/785 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3221 ,  H01L21/76232 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/32 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

摘要： A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the PAI region to form a dislocation plane. The dislocation plane is formed as a result of the annealing, with a tilt angle of the dislocation plane being smaller than about 65 degrees.

摘要翻译： 一种方法包括形成金属氧化物半导体场效应晶体管（MOSFET）。 该方法包括进行注入以形成与MOSFET的栅电极相邻的预非晶化注入（PAI）区域，在PAI区域上形成应变封盖层，并对应变封盖层和PAI区域进行退火 形成位错平面。 作为退火的结果形成位错平面，位错面的倾斜角小于约65度。

公开(公告)号：US20140183707A1

公开(公告)日：2014-07-03

申请号：US14101451

申请日：2013-12-10

申请人： Texas Instruments Incorporated

发明人： James Fred SALZMAN ,  Charles Clayton HADSELL

IPC分类号： H01L27/02 ,  H01L21/82 ,  H01L21/74 ,  H01L21/02

CPC分类号： H01L29/0638 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/74 ,  H01L21/82 ,  H01L21/823412 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/088 ,  H01L27/0921 ,  H01L29/0688 ,  H01L29/1079 ,  H01L29/78

摘要： An integrated circuit is formed by providing a heavily doped substrate of a first conductivity type, forming a lightly doped lower epitaxial layer of the first conductivity type over the substrate, implanting dopants of the first conductivity type into the lower epitaxial layer in an area for a shallow component and blocking the dopants from an area for a deep component, forming a lightly doped upper epitaxial layer over the lower epitaxial layer and activating the implanted dopants to form a heavily doped region. The shallow component is formed over the heavily doped region, and the deep component is formed outside the heavily doped region, extending through the upper epitaxial layer into the lower epitaxial layer.

摘要翻译： 通过提供第一导电类型的重掺杂衬底形成集成电路，在衬底上形成第一导电类型的轻掺杂的下外延层，将第一导电类型的掺杂剂注入到用于 并且从深部分的区域阻挡掺杂剂，在下部外延层上形成轻掺杂的上部外延层，并激活注入的掺杂剂以形成重掺杂区域。 在重掺杂区域上形成浅分量，并且深部分形成在重掺杂区域的外部，延伸穿过上部外延层进入下部外延层。

公开(公告)号：US20140177312A1

公开(公告)日：2014-06-26

申请号：US14234479

申请日：2011-07-29

申请人： Ken Shibata ,  Yuta Yanagitani

发明人： Ken Shibata ,  Yuta Yanagitani

IPC分类号： H01L27/11 ,  G11C11/412

CPC分类号： H01L27/1104 ,  G11C5/14 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1116 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/42356

摘要： A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.

摘要翻译： 具有高自由度布置的半导体器件具有第一部分AR1，其中多个p型阱PW和n型阱NW沿着X轴方向交替布置成彼此相邻。 多个井PW的公共供电区域（ARP2）布置在一侧，以将AR1插入Y轴方向，并且用于多个井NW的公共供电区域（ARN2）布置在 另一边。 在PW阱的供电区域（ARP2）中，形成具有沿X轴方向延伸的细长形状的p +型供电扩散层P +（DFW）。 在AR1中布置有沿X轴方向延伸以跨越PW和NW阱之间的边界的多个栅极层GT，并且相应地形成多个MIS晶体管。

公开(公告)号：US08735238B2

公开(公告)日：2014-05-27

申请号：US13039525

申请日：2011-03-03

申请人： ChanSam Chang ,  Shigenobu Maeda ,  HeonJong Shin ,  ChangBong Oh

发明人： ChanSam Chang ,  Shigenobu Maeda ,  HeonJong Shin ,  ChangBong Oh

IPC分类号： H01L21/8238

CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0692 ,  H01L29/1079 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

摘要： Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well.

摘要翻译： 公开了使用减少数量的处理步骤在公共基板上形成高压和低压晶体管的方法和装置。 一种示例性方法包括使用第一掩模和第一注入工艺同时注入在至少第一高电压晶体管阱和第一低电压晶体管阱上形成阱，所述公共衬底由隔离结构隔开，所述隔离结构将第一深度延伸到衬底中 第一导电类型的掺杂材料进入低压晶体管阱的沟道区域和用于高压晶体管阱的漏极区域。

公开(公告)号：US20140084246A1

公开(公告)日：2014-03-27

申请号：US13629178

申请日：2012-09-27

申请人： Ravi Pillarisetty ,  Niti Goel ,  Han Wui Then ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Benjamin Chu-Kung

发明人： Ravi Pillarisetty ,  Niti Goel ,  Han Wui Then ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Benjamin Chu-Kung

IPC分类号： H01L29/78 ,  H01L29/775

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/785 ,  H01L29/78696

摘要： Semiconductor devices having germanium active layers with underlying parasitic leakage barrier layers are described. For example, a semiconductor device includes a first buffer layer disposed above a substrate. A parasitic leakage barrier is disposed above the first buffer layer. A second buffer layer is disposed above the parasitic leakage barrier. A germanium active layer is disposed above the second buffer layer. A gate electrode stack is disposed above the germanium active layer. Source and drain regions are disposed above the parasitic leakage barrier, on either side of the gate electrode stack.

摘要翻译： 描述具有底层寄生泄漏阻挡层的具有锗活性层的半导体器件。 例如，半导体器件包括设置在衬底上方的第一缓冲层。 寄生泄漏屏障设置在第一缓冲层之上。 第二缓冲层设置在寄生泄漏屏障的上方。 锗活性层设置在第二缓冲层上方。 栅电极堆叠设置在锗活性层上方。 源极和漏极区域设置在栅极电极堆叠的任一侧上的寄生泄漏屏障之上。