公开(公告)号：US20180108864A1

公开(公告)日：2018-04-19

申请号：US15728707

申请日：2017-10-10

Applicant: Japan Display Inc.

Inventor： Masumi NISHIMURA ,  Heisuke Kanaya

IPC: H01L51/52 ,  H01L51/00 ,  H01L27/32

CPC classification number: H01L51/5253 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1274 ,  H01L27/3246 ,  H01L27/3262 ,  H01L29/42384 ,  H01L29/78675 ,  H01L51/0097 ,  H01L51/5225 ,  H01L2029/42388 ,  H01L2227/326 ,  H01L2251/5338 ,  H01L2251/558

Abstract: The purpose of the present invention is to realize a reliable bendable organic EL display device with high reliability. The structure of the invention is as follows. An organic EL display device comprising: pixels, each of the pixels has an emitting layer, which is sandwiched by a lower electrode and an upper electrode, a first inorganic protective film is formed on the emitting layer, the first inorganic protective film is circle or polygon having at least five sides, in a plan view.

公开(公告)号：US09947736B2

公开(公告)日：2018-04-17

申请号：US15340948

申请日：2016-11-01

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.

Inventor： Yuanjun Hsu

IPC: H01L27/32 ,  H01L29/45 ,  H01L27/12 ,  H01L51/56 ,  H01L29/49 ,  H01L21/02 ,  H01L29/786 ,  H01L21/306 ,  H01L29/66 ,  H01L51/52 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L27/3262 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02675 ,  H01L21/30604 ,  H01L27/1222 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3265 ,  H01L29/41775 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/66757 ,  H01L29/7833 ,  H01L29/78603 ,  H01L29/78675 ,  H01L29/78696 ,  H01L51/5215 ,  H01L51/56 ,  H01L2227/323 ,  H01L2251/301 ,  H01L2251/306 ,  H01L2251/308

Abstract: An AMOLED back plate includes a substrate on which a buffer layer and a poly-silicon section are sequentially formed. A source and a drain are respectively formed of P-type heavy doped micro silicon on the poly-silicon section that have edges facing and spaced from each other to define a channel therebetween. A gate isolation layer is formed on the buffer layer, the source, the drain and the channel. A gate is formed on the gate isolation layer and has opposite edges that face in directions toward the edges of the source and the drain. The opposite edges of the gate are spaced from the edges of the source and the drain by predetermined spacing distance in horizontal directions so as to prevent the gate from overlapping the source and the drain.

公开(公告)号：US20180097122A1

公开(公告)日：2018-04-05

申请号：US15101029

申请日：2016-05-09

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd

Inventor： Jinquan DENG

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/78675 ,  H01L27/1288 ,  H01L29/1041 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863

Abstract: A thin film transistor, a manufacture method of a thin film transistor and a CMOS device are provided. The thin film transistor includes: a substrate and a low temperature poly-silicon (LTPS) layer disposed on the same side of the substrate, a first and a second light doped zones disposed adjacently to two opposite ends of the LTPS on the same layer with the LTPS, a first heavy doped zone disposed on the same layer with the LTPS, the first heavy doped zone is disposed adjacently to an end of the first light doped zone away from the LTPS, the second heavy doped zone is disposed adjacently to an end of the second light doped zone away from the LTPS, the first insulating layer, covering the first and the second light doped zones as well as the first and the second heavy doped zones.

公开(公告)号：US20180083142A1

公开(公告)日：2018-03-22

申请号：US15106812

申请日：2016-04-26

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.

Inventor： Shipeng Chi

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/78645 ,  H01L27/1222 ,  H01L27/1274 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/08 ,  H01L29/423 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78675 ,  H01L29/78696

Abstract: The present invention provides a manufacture method of a TFT substrate and a manufactured TFT substrate. In the manufacture method of the TFT substrate according to the present invention, by locating the first lightly doped offset region and the second lightly doped offset region in the TFT, the off state current of the TFT can be reduced; meanwhile, by utilizing the first gate and the second gate to compose the dual gate structure, the influence of the first lightly doped offset region and the second lightly doped offset region to the TFT on state current can be reduced, and the first gate and the second gate are connected, and controlled by the same gate voltage, and no additional voltage is required; the structure is simple and the electrical property is excellent, and the manufactured TFT substrate possesses the better electrical property.

公开(公告)号：US20180083084A1

公开(公告)日：2018-03-22

申请号：US15684452

申请日：2017-08-23

Applicant: Samsung Display Co., Ltd.

Inventor： Jaybum KIM ,  Kyoungseok SON ,  Jihun LIM ,  Eoksu KIM ,  Junhyung LIM

IPC: H01L27/32

CPC classification number: H01L27/3262 ,  G09G3/3225 ,  G09G3/3266 ,  G09G3/3275 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2330/02 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3265 ,  H01L29/78675 ,  H01L29/7869 ,  H01L2227/323

Abstract: A semiconductor device includes a base substrate, a first transistor including a first semiconductor pattern, a first control electrode, a first input electrode, and a first output electrode, each of which is disposed on the base substrate, a second transistor including a second semiconductor pattern, a second control electrode, a second input electrode, and a second output electrode, and a plurality of insulating layers. A single first through part exposes the first control electrode and the first semiconductor pattern disposed on both sides of the first control electrode.

公开(公告)号：US20180083052A1

公开(公告)日：2018-03-22

申请号：US15823514

申请日：2017-11-27

Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd.

Inventor： Xiaoxing Zhang

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/32

CPC classification number: H01L27/1296 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1262 ,  H01L27/1274 ,  H01L27/1281 ,  H01L27/3262 ,  H01L29/78675 ,  H01L29/78696

Abstract: A method for manufacturing a LTPS TFT substrate is provided. Buffer layers are respectively provided in a drive TFT area and a display TFT area and have different thicknesses, such that the thickness of the buffer layer in the drive TFT area is larger than the thickness of the buffer layer in the display TFT area so that different temperature grades are formed in a crystallization process of poly-silicon to achieve control of the grain diameters of crystals. A poly-silicon layer that is formed in the drive TFT area in the crystallization process has a large lattice dimension to increase electron mobility thereof. Fractured crystals can be formed in a poly-silicon layer of the display TFT area in the crystallization process for ensuring the uniformity of the grain boundary and increasing the uniformity of electrical current. Accordingly, the electrical property demands for different TFTs can be satisfied.

公开(公告)号：US20180082843A1

公开(公告)日：2018-03-22

申请号：US15463446

申请日：2017-03-20

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tatsunori ISOGAI

IPC: H01L21/225 ,  H01L27/12 ,  H01L29/786 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L29/10 ,  H01L21/324 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/2255 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/324 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/124 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/78675 ,  H01L29/78696

Abstract: In a manufacturing method of a semiconductor device according to an embodiment, an oxide film is formed on a semiconductor layer containing an impurity. A heat treatment is performed on the semiconductor layer to diffuse part of the impurity into the oxide film with hydrogen plasma treatment on the oxide film or with ultraviolet irradiation on the oxide film. After the heat treatment, the oxide film is removed.

公开(公告)号：US20180076239A1

公开(公告)日：2018-03-15

申请号：US15678501

申请日：2017-08-16

Applicant: Japan Display Inc.

Inventor： Isao SUZUMURA ,  Hajime Watakabe ,  Akihiro Hanada ,  Hirokazu Watanabe

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L27/1251 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13685 ,  G02F2202/104 ,  H01L21/02532 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/02675 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1229 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/127 ,  H01L27/1274 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78675 ,  H01L29/78693 ,  H01L2227/323

Abstract: The purpose of the present invention is to form both LTPS TFT and Ply-Si TFT on a same substrate. The feature of the display device to realize the above purpose is that: a display device comprising: a substrate including a first TFT having an oxide semiconductor layer and a second TFT having a Poly-Si layer, an undercoat is formed on the substrate, the oxide semiconductor layer is formed on or above the undercoat, a first interlayer insulating film is formed on or above the oxide semiconductor layer, the Poly-Si layer is formed on or above the first interlayer insulating film.

公开(公告)号：US20180061920A1

公开(公告)日：2018-03-01

申请号：US15683121

申请日：2017-08-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： KYOUNGSEOK SON ,  JAYBUM KIM ,  EOKSU KIM ,  JUNHYUNG LIM ,  JIHUN LIM

IPC: H01L27/32 ,  H01L29/786 ,  H01L29/66 ,  H01L21/4757 ,  H01L21/02

CPC classification number: H01L27/3262 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/47573 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/3258 ,  H01L27/3265 ,  H01L28/60 ,  H01L29/24 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78675 ,  H01L29/7869 ,  H01L2227/323

Abstract: A method of manufacturing a semiconductor device. A pre first semiconductor pattern having a crystalline semiconductor material is formed on a base substrate. A pre first insulation layer is formed on the pre first semiconductor pattern. A first semiconductor pattern is formed by defining a channel region in the pre first semiconductor pattern. A pre protection layer is formed on the pre first insulation layer. A pre second semiconductor pattern including an oxide semiconductor material is formed on the pre protection layer. A pre second insulation layer is formed on the pre second semiconductor pattern. The pre second insulation layer is patterned using an etching gas such that at least a portion of the pre second semiconductor pattern is exposed. A second semiconductor pattern is formed by defining a channel region in the pre second semiconductor pattern. The pre protection layer has a material with a first etch selectivity that is different from a second etch selectivity of the second insulation layer with respect to the etching gas.

公开(公告)号：US09905624B2

公开(公告)日：2018-02-27

申请号：US15433007

申请日：2017-02-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Makoto Udagawa ,  Masahiko Hayakawa ,  Jun Koyama ,  Mitsuaki Osame ,  Aya Anzai

IPC: H01L27/32 ,  H01L29/786 ,  H01L51/52 ,  H01L27/12

CPC classification number: H01L27/3262 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/3276 ,  H01L29/78675 ,  H01L29/78696 ,  H01L51/52

Abstract: The present invention provides a TFT that has a channel length particularly longer than that of an existing one, specifically, several tens to several hundreds times longer than that of the existing one, and thereby allowing turning to an on-state at a gate voltage particularly higher than the existing one and driving, and allowing having a low channel conductance gd. According to the present invention, not only the simple dispersion of on-current but also the normalized dispersion thereof can be reduced, and other than the reduction of the dispersion between the individual TFTs, the dispersion of the OLEDs themselves and the dispersion due to the deterioration of the OLED can be reduced.