公开(公告)号：US20120223322A1

公开(公告)日：2012-09-06

申请号：US13053646

申请日：2011-03-22

申请人： Heny Lin ,  Jason Zhang ,  Alberto Guerra

发明人： Heny Lin ,  Jason Zhang ,  Alberto Guerra

IPC分类号： H01L29/20

CPC分类号： H01L27/0727 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/065 ,  H01L25/18 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/778 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48147 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014

摘要： One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

摘要翻译： 一个示例性的公开的实施例包括二端子堆叠管芯封装，其包括二极管，例如硅二极管，堆叠在III族氮化物晶体管的顶部，使得二极管的阴极位于III的源极上并与其电耦合 氮化晶体管。 封装的第一端子耦合到III族氮化物晶体管的漏极，并且封装的第二端子耦合到二极管的阳极。 以这种方式，诸如级联整流器的器件可以以堆叠的管芯形式封装，与常规封装相比，导致减小的寄生电感和电阻，改善的散热，更小的外形尺寸以及更低的制造成本。

公开(公告)号：US20120168925A1

公开(公告)日：2012-07-05

申请号：US13095650

申请日：2011-04-27

申请人： Eung San Cho ,  Chuan Cheah

发明人： Eung San Cho ,  Chuan Cheah

IPC分类号： H01L23/495

CPC分类号： H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/165 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a leadframe, a flip chip driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. The source of the control transistor is electrically coupled to the drain of the sync transistor using the leadframe and one of the transistor conductive clips. In this manner, the leadframe and the conductive clips provide efficient current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

摘要翻译： 一个示例性的公开的实施例包括被配置为具有控制晶体管和设置在引线框上的同步晶体管的降压转换器的大功率半导体封装，用于驱动控制和同步晶体管的倒装芯片驱动器集成电路（IC） 晶体管的顶表面到衬底焊盘，例如引线框焊盘。 使用引线框和晶体管导电夹中的一个，控制晶体管的源极电耦合到同步晶体管的漏极。 以这种方式，引线框架和导电夹子通过直接机械连接和大的表面积传导提供有效的电流传导，从而与使用引线键合的常规封装方法相比，能够实现具有显着降低的电阻，形状因子，复杂性和成本的封装 晶体管互连。

公开(公告)号：US20120168924A1

公开(公告)日：2012-07-05

申请号：US13095527

申请日：2011-04-27

申请人： Eung San Cho ,  Chuan Cheah

发明人： Eung San Cho ,  Chuan Cheah

IPC分类号： H01L23/495

CPC分类号： H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/165 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

摘要翻译： 一个示例性的公开的实施例包括被配置为具有控制晶体管和设置在公共引线框焊盘上的同步晶体管的降压转换器的高功率半导体封装，用于驱动控制和同步晶体管的驱动器集成电路（IC） 晶体管的顶表面到衬底焊盘，例如引线框焊盘。 以这种方式，引线框架和导电夹子通过直接机械连接和大的表面积传导提供有效的接地或电流传导，从而与使用以下的传统封装方法相比，能够实现具有显着降低的电阻，形状因素，复杂性和成本的封装 用于晶体管互连的引线。

公开(公告)号：US11710662B2

公开(公告)日：2023-07-25

申请号：US17029699

申请日：2020-09-23

申请人： United Silicon Carbide, Inc.

发明人： Anup Bhalla ,  Leonid Fursin

IPC分类号： H01L29/06 ,  H01L21/78 ,  H01L23/00

CPC分类号： H01L21/7813 ,  H01L24/98 ,  H01L2924/1033 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/10323 ,  H01L2924/10325

摘要： Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.

公开(公告)号：US20180166359A1

公开(公告)日：2018-06-14

申请号：US15423086

申请日：2017-02-02

申请人： Toyota Motor Engineering & Manufacturing North America, Inc.

发明人： Yuji Fukuoka

IPC分类号： H01L23/473 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L23/473 ,  H01L23/367 ,  H01L23/3738 ,  H01L24/32 ,  H01L2224/32221 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48221 ,  H01L2224/73265 ,  H01L2924/10155 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/10323 ,  H01L2924/10325 ,  H01L2924/1033 ,  H01L2924/00014

摘要： An electronics assembly comprises a semiconductor device having a first device surface and at least one device conductive layer disposed on the first device surface. A cooling structure is coupled to the semiconductor device. The cooling structure comprises a first cooling structure surface and a second cooling structure surface. The second cooling structure surface is opposite from the first cooling structure surface and the first cooling structure surface is coupled to the semiconductor device. One side cooling structure surface is transverse to the respective first and second cooling structure surface. The one side electrode is disposed on the at least one side cooling structure surface in which the at least one side electrode is electrically coupled to the at least one device conductive layer. The cooling structure includes a fluid inlet for receiving a cooling fluid and a fluid outlet for removing the cooling fluid from the cooling structure.

公开(公告)号：US20180145048A1

公开(公告)日：2018-05-24

申请号：US15875335

申请日：2018-01-19

申请人： EV GROUP E. THALLNER GMBH

发明人： Markus WIMPLINGER

IPC分类号： H01L23/00 ,  B81C3/00

CPC分类号： H01L24/83 ,  B81C3/001 ,  B81C2203/036 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29105 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29117 ,  H01L2224/29118 ,  H01L2224/29123 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29157 ,  H01L2224/2916 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29184 ,  H01L2224/32145 ,  H01L2224/32507 ,  H01L2224/8302 ,  H01L2224/83022 ,  H01L2224/8381 ,  H01L2224/83894 ,  H01L2924/01003 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01034 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01055 ,  H01L2924/01056 ,  H01L2924/01322 ,  H01L2924/10251 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1026 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10323 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10334 ,  H01L2924/10335 ,  H01L2924/10336 ,  H01L2924/10346 ,  H01L2924/1037 ,  H01L2924/10371 ,  H01L2924/10372 ,  H01L2924/10373 ,  H01L2924/10375 ,  H01L2924/10376 ,  H01L2924/10377 ,  H01L2924/10821 ,  H01L2924/10823 ,  H01L2924/10831 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/01013 ,  H01L2924/01031 ,  H01L2924/0103

摘要： A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.

公开(公告)号：US09911713B2

公开(公告)日：2018-03-06

申请号：US15441741

申请日：2017-02-24

申请人： EV GROUP E. THALLNER GMBH

发明人： Markus Wimplinger

IPC分类号： H01L23/00 ,  B81C3/00

CPC分类号： H01L24/83 ,  B81C3/001 ,  B81C2203/036 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29105 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29117 ,  H01L2224/29118 ,  H01L2224/29123 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29157 ,  H01L2224/2916 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29184 ,  H01L2224/32145 ,  H01L2224/32507 ,  H01L2224/8302 ,  H01L2224/83022 ,  H01L2224/8381 ,  H01L2224/83894 ,  H01L2924/01003 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01034 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01055 ,  H01L2924/01056 ,  H01L2924/01322 ,  H01L2924/10251 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1026 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10323 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10334 ,  H01L2924/10335 ,  H01L2924/10336 ,  H01L2924/10346 ,  H01L2924/1037 ,  H01L2924/10371 ,  H01L2924/10372 ,  H01L2924/10373 ,  H01L2924/10375 ,  H01L2924/10376 ,  H01L2924/10377 ,  H01L2924/10821 ,  H01L2924/10823 ,  H01L2924/10831 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/01013 ,  H01L2924/01031 ,  H01L2924/0103

摘要： A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.

公开(公告)号：US20170162684A1

公开(公告)日：2017-06-08

申请号：US15440404

申请日：2017-02-23

申请人： Transphorm Inc.

发明人： Rakesh K. Lal

IPC分类号： H01L29/778 ,  H01L27/06 ,  H01L27/088 ,  H01L21/8252 ,  H01L29/417 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20 ,  H01L23/535

CPC分类号： H01L29/7787 ,  H01L21/0217 ,  H01L21/0254 ,  H01L21/8252 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/535 ,  H01L24/48 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/085 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/78 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2924/00014 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/00 ,  H01L2224/45099

摘要： A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

公开(公告)号：US09673109B2

公开(公告)日：2017-06-06

申请号：US15019318

申请日：2016-02-09

申请人： Infineon Technologies Americas Corp.

发明人： Eung San Cho ,  Andrew N. Sawle ,  Mark Pavier ,  Daniel Cutler

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/84 ,  H01L25/00 ,  H01L23/495 ,  H01L25/18 ,  H01L23/00 ,  H01L25/07 ,  H01L25/11 ,  H01L25/16 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L21/84 ,  H01L21/4825 ,  H01L21/4871 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/072 ,  H01L25/117 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16245 ,  H01L2224/24137 ,  H01L2224/24245 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/92224 ,  H01L2224/92244 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/10325 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10341 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/10355 ,  H01L2924/10356 ,  H01L2924/10357 ,  H01L2924/10358 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

摘要： In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

公开(公告)号：US09530774B2

公开(公告)日：2016-12-27

申请号：US14620596

申请日：2015-02-12

申请人： Infineon Technologies Americas Corp.

发明人： Heny Lin ,  Jason Zhang ,  Alberto Guerra

IPC分类号： H01L25/065 ,  H01L27/07 ,  H01L23/495 ,  H01L25/18 ,  H01L29/20 ,  H01L27/06 ,  H01L23/00 ,  H01L29/778

CPC分类号： H01L27/0727 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/065 ,  H01L25/18 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/778 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48147 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014

摘要： One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

摘要翻译： 一个示例性的公开的实施例包括二端子堆叠管芯封装，其包括二极管，例如硅二极管，堆叠在III族氮化物晶体管的顶部，使得二极管的阴极位于III的源极上并与其电耦合 氮化晶体管。 封装的第一端子耦合到III族氮化物晶体管的漏极，并且封装的第二端子耦合到二极管的阳极。 以这种方式，诸如级联整流器的器件可以以堆叠的管芯形式封装，与常规封装相比，导致减小的寄生电感和电阻，改善的散热，更小的外形尺寸以及更低的制造成本。