公开(公告)号：US20200227640A1

公开(公告)日：2020-07-16

申请号：US16832282

申请日：2020-03-27

申请人： LG INNTEK CO., LTD.

发明人： Dong Mug SEONG ,  Jong Min YUN ,  Su Hyeon CHO ,  Hae Sik KIM ,  Tae Hoon HAN ,  Hyo Won SON ,  Sang Yu LEE ,  Sang Beum LEE

IPC分类号： H01L51/00 ,  C23C14/04 ,  C23F1/02 ,  H01L21/027 ,  H01L21/203 ,  H01L51/56 ,  H01L21/475

摘要： A metal plate to be used in the manufacture of a deposition mask comprises: a base metal plate; and a surface layer disposed on the base metal plate, wherein the surface layer includes elements different from those of the base metal plate, or has a composition ratio different from that of the base metal plate, and an etching rate of the base metal plate is greater than the etching rate of the surface layer. An embodiment includes a manufacturing method for a deposition mask having an etching factor greater than or equal to 2.5. The deposition mask of the embodiment includes a deposition pattern region and a non-deposition region, the deposition pattern region includes a plurality of through-holes, the deposition pattern region is divided into an effective region, a peripheral region, and a non-effective region, and through-holes can be formed in the effective region and the peripheral region.

公开(公告)号：US20200227553A1

公开(公告)日：2020-07-16

申请号：US16832386

申请日：2020-03-27

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio MASUOKA ,  Nozomu HARADA

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/461 ,  H01L21/475 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/417 ,  H01L29/786

摘要： An SGT is formed that includes Si pillars. The SGT includes WSi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.

公开(公告)号：US10580649B2

公开(公告)日：2020-03-03

申请号：US15447807

申请日：2017-03-02

申请人： MicroContinuum Inc.

发明人： W. Dennis Slafer

IPC分类号： H01L21/027 ,  H01L27/142 ,  H01L31/18 ,  H01L21/467 ,  H01L21/311 ,  H01L21/475 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/32 ,  H01L21/47 ,  H01L51/00 ,  H01L31/0352 ,  H01L31/108 ,  H01Q1/24

摘要： The present disclosure advances the art by providing a method and system for forming electronic devices. In particular, and by example only, methods are described for forming devices for harvesting energy in the terahertz frequency range on flexible substrates, wherein the methods provide favorable accuracy in registration of the various device elements and facilitate low-cost R2R manufacturing.

公开(公告)号：US10403646B2

公开(公告)日：2019-09-03

申请号：US15041502

申请日：2016-02-11

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Hideomi Suzawa ,  Yuta Endo ,  Kazuya Hanaoka

IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L21/475 ,  H01L21/4757

摘要： A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a first insulating layer; a first oxide layer over the first insulating layer; a semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer over the semiconductor layer; a second insulating layer over the first insulating layer; a third insulating layer over the second insulating layer, the source electrode layer, and the drain electrode layer; a second oxide layer over the semiconductor layer; a gate insulating layer over the second oxide layer; a gate electrode layer over the gate insulating layer; and a fourth insulating layer over the third insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer.

公开(公告)号：US10396206B2

公开(公告)日：2019-08-27

申请号：US15643940

申请日：2017-07-07

申请人： GLOBALFOUNDRIES INC.

发明人： Ashish Kumar Jha ,  Haiting Wang ,  Wei Hong ,  Wei Zhao ,  Tae Jeong Lee ,  Zhenyu Hu

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/027 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/3205 ,  H01L29/66 ,  H01L21/475 ,  H01L29/43 ,  H01L27/02 ,  H01L27/118

摘要： A method of manufacturing a semiconductor device includes the formation of an oxide spacer layer to modify the critical dimension of a gate cut opening in connection with a replacement metal gate process. The oxide spacer layer is deposited after etching a gate cut opening in an overlying hard mask such that the oxide spacer layer is deposited onto sidewall surfaces of the hard mask within the opening and directly over the top surface of a sacrificial gate. The oxide spacer may also be deposited into recessed regions within an interlayer dielectric located adjacent to the sacrificial gate. By filling the recessed regions with an oxide, the opening of trenches through the oxide spacer layer and the interlayer dielectric to expose source/drain junctions can be simplified.

公开(公告)号：US20190035633A1

公开(公告)日：2019-01-31

申请号：US15665183

申请日：2017-07-31

申请人： GLOBALFOUNDRIES, Inc.

发明人： Ashish Kumar Jha ,  Hui Zhan ,  Hong Yu ,  Zhenyu Hu ,  Haiting Wang ,  Edward Reis ,  Charles Vanleuvan

IPC分类号： H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/475

摘要： A shallow trench isolation (STI) structure is formed from a conventional STI trench structure formed of first dielectric material extending into the substrate. The conventional STI structure undergoes further processing, including removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride layer is formed above remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses. The nitride layer provides an “inner spacer” between the first insulating material and the second insulating material and also separates the substrate from the second insulating material. An isotropic Fin reveal process is performed and the STI structure assists in equalizing fin heights and increasing active S/D region area/volume.

公开(公告)号：US20180233379A1

公开(公告)日：2018-08-16

申请号：US15569759

申请日：2017-03-22

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Zhidong Yuan

IPC分类号： H01L21/48 ,  G09G3/20 ,  H01L21/02 ,  H01L21/47 ,  H01L21/4757 ,  H01L21/475 ,  H01L29/417

CPC分类号： H01L21/486 ,  G09G3/20 ,  H01L21/02345 ,  H01L21/47 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/768 ,  H01L21/77 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/41733

摘要： The present disclosure provides a method of forming a via hole, an array substrate and a method of forming the same and a display device. The method of forming a via hole includes: forming a pattern of a first via hole and a pattern of an upper-part etched structure of a second via hole simultaneously on a base substrate through a first patterning process by using a first mask; forming a pattern of the second hole in a region corresponding to the formed pattern of the upper-part etched structure of the second via hole through a second patterning process by using a second mask.

公开(公告)号：US09875965B2

公开(公告)日：2018-01-23

申请号：US15210623

申请日：2016-07-14

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Guangcai Fu ,  Tianlun Yang ,  Xiaoping Zhang

IPC分类号： H01L23/48 ,  H01L23/528 ,  B81C1/00 ,  H01L21/475 ,  B81B7/00 ,  H01L21/02 ,  H01L23/532 ,  H01L29/06

CPC分类号： H01L23/5283 ,  B81B7/007 ,  B81B2201/0264 ,  B81B2207/07 ,  B81C1/00095 ,  B81C1/00849 ,  B81C2201/0132 ,  H01L21/02068 ,  H01L21/475 ,  H01L23/53219 ,  H01L23/53233 ,  H01L23/53247 ,  H01L29/0649 ,  H01L2221/1063

摘要： Semiconductor devices and fabrication methods are provided. In a semiconductor device, a semiconductor substrate includes a first electrode layer having a top surface coplanar with a top surface of the semiconductor substrate. A sacrificial layer is formed on the semiconductor substrate and the first electrode layer. A first mask layer made of a conductive material is formed on the sacrificial layer. The first mask layer and the sacrificial layer are etched until a surface of the first electrode layer is exposed to form openings through the first mask layer and the sacrificial layer. A cleaning process is performed to remove etch byproducts adhered to a surface of the first mask layer and adhered to sidewalls and bottom surfaces of the openings. Conductive plugs are formed in the openings after the cleaning process.

公开(公告)号：US20170316953A1

公开(公告)日：2017-11-02

申请号：US15521246

申请日：2014-10-31

申请人： SHENZHEN GRADUATE SCHOOL, PEKING UNIVERSITY

发明人： Shengdong ZHANG ,  Yang SHAO ,  Xiang XIAO ,  Xin HE

IPC分类号： H01L21/473 ,  H01L29/786 ,  H01L29/66 ,  H01L21/475 ,  H01L21/02 ,  H01L21/443

CPC分类号： H01L21/473 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/28 ,  H01L21/443 ,  H01L21/475 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

摘要： A method for fabricating a metal oxide thin film transistor comprises selecting a substrate and fabricating a gate electrode thereon; growing a layer of dielectric or high permittivity dielectric on the substrate to serve as a gate dielectric layer; growing a first metal layer on the gate dielectric layer and a second metal layer on the first metal layer; fabricating a channel region at a middle position of the first metal layer and a passivation region at a middle position of the second metal layer; anodizing the metals of the passivation region and the channel region at atmospheric pressure and room temperature; fabricating a source and a drain; forming an active region comprising the source, the drain, and the channel region; depositing a silicon nitride layer on the active region; fabricating two electrode contact holes; depositing a metal aluminum film; and fabricating two metal contact electrodes by photolithography and etching.

公开(公告)号：US09735154B2

公开(公告)日：2017-08-15

申请号：US14918012

申请日：2015-10-20

申请人： GLOBALFOUNDRIES Inc.

发明人： Andy Chih-Hung Wei ,  Dae-han Choi ,  Dae Geun Yang ,  Xiang Hu ,  Mariappan Hariharaputhiran

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L21/308 ,  H01L21/311 ,  H01L21/306 ,  H01L21/762 ,  H01L21/033 ,  H01L21/475 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06

CPC分类号： H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/475 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

摘要： Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.