公开(公告)号：US20160315253A1

公开(公告)日：2016-10-27

申请号：US15147682

申请日：2016-05-05

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Sanjeev Aggarwal ,  Kerry Joseph Nagel ,  Chaitanya Mudivarthi ,  Nicholas Rizzo ,  Jason Allen Janesky

IPC: H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: In forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device.

公开(公告)号：US09444037B2

公开(公告)日：2016-09-13

申请号：US15043633

申请日：2016-02-15

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jason Janesky ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/02 ,  B82Y10/00 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  Y10S977/935

Abstract: A magnetoresistive memory array including a plurality of magnetoresistive memory elements wherein each magnetoresistive memory element comprises a free layer including at least one ferromagnetic layer having perpendicular magnetic anisotropy, a fixed layer, and a tunnel barrier, disposed between and in contact with the free and fixed layers. The tunnel barrier includes a first metal-oxide layer, having a thickness between 1 and 10 Angstroms, a second metal-oxide layer, having a thickness between 3 and 6 Angstroms, disposed on the first metal-oxide layer, and a third metal-oxide layer, having a thickness between 3 and 6 Angstroms, disposed over the second metal-oxide layer. In one embodiment, the third metal-oxide layer is in contact with the free layer or fixed layer. The tunnel barrier may also include a fourth metal-oxide layer, having a thickness between 1 and 10 Angstroms, disposed between the second and third metal-oxide layers.

Abstract translation: 一种包括多个磁阻存储元件的磁阻存储器阵列，其中每个磁阻存储元件包括自由层，该自由层包括至少一个具有垂直磁各向异性的铁磁层，固定层和隧道势垒，该自由层设置在自由和固定 层。 隧道势垒包括设置在第一金属氧化物层上的第一金属氧化物层，其厚度为1至10埃，厚度为3埃至6埃的第二金属氧化物层，以及第三金属氧化物层， 氧化物层，其厚度为3埃至6埃，设置在第二金属氧化物层上。 在一个实施例中，第三金属氧化物层与自由层或固定层接触。 隧道势垒还可以包括设置在第二和第三金属氧化物层之间的厚度在1埃和10埃之间的第四金属氧化物层。

公开(公告)号：US20160254041A1

公开(公告)日：2016-09-01

申请号：US15149826

申请日：2016-05-09

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C11/1673 ,  G06F11/1068 ,  G09C1/00 ,  G11C5/06 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C14/0081 ,  G11C14/009 ,  G11C29/52 ,  G11C2213/75 ,  G11C2213/77 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H04L9/0866

Abstract: In some examples, a nonvolatile storage element may be configured to store a state or value during a low power or powered down period of a circuit. For example, the nonvolatile storage element may include a bridge of resistive elements that have a resistive state that may be configured by applying voltages to multiple drive paths. A sense amplifier may be connected to the bridge in order to resolve a voltage differential associated with the bridge to ether power or ground and, thereby determine the state associated with on the nonvolatile storage element.

公开(公告)号：US09391264B2

公开(公告)日：2016-07-12

申请号：US14727910

申请日：2015-06-02

Applicant: Everspin Technologies, Inc.

Inventor： Srinivas V. Pietambaram ,  Bengt J. Akerman ,  Renu Whig ,  Jason A. Janesky ,  Nicholas D. Rizzo ,  Jon M. Slaughter

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10

Abstract: An MRAM bit includes a free magnetic region, a fixed magnetic region comprising an anti-ferromagnetic material, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, wherein the one or more ferromagnetic materials includes cobalt, (ii) a second layer of one or more ferromagnetic materials wherein the one or more ferromagnetic materials includes cobalt, (iii) a third layer of one or more ferromagnetic materials, and an anti-ferromagnetic coupling layer, wherein: (a) the anti-ferromagnetic coupling layer is disposed between the first and third layers, and (b) the second layer is disposed between the first layer and the anti-ferromagnetic coupling layer.

Abstract translation: MRAM位包括自由磁区，包括反铁磁材料的固定磁区和位于自由磁区与固定磁区之间的电介质层。 在一个方面，固定磁区基本上由未固定的固定合成反铁磁（SAF）结构组成，其包括（i）一个或多个铁磁材料的第一层，其中一个或多个铁磁材料包括钴，（ii ）一种或多种铁磁材料的第二层，其中所述一种或多种铁磁材料包括钴，（iii）一种或多种铁磁材料的第三层和反铁磁性耦合层，其中：（a）所述反铁磁性材料 耦合层设置在第一和第三层之间，（b）第二层设置在第一层和反铁磁性耦合层之间。

公开(公告)号：US09378796B2

公开(公告)日：2016-06-28

申请号：US14580379

申请日：2014-12-23

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/15

CPC classification number: G11C11/1675 ,  G11C11/15 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673

Abstract: A method of applying a write current to a magnetic tunnel junction device minimizes sub-threshold leakage. NMOS- and PMOS-follower circuits are used in applying the write current, and bias signals for the follower circuits are isolated from global bias signals before the write current is applied.

Abstract translation: 向磁性隧道结装置施加写入电流的方法使得亚阈值泄漏最小化。 NMOS和PMOS跟随器电路用于施加写入电流，并且在施加写入电流之前，跟随器电路的偏置信号与全局偏置信号隔离。

公开(公告)号：US20160163964A1

公开(公告)日：2016-06-09

申请号：US15046483

申请日：2016-02-18

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jijun Sun ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine ,  Frederick Mancoff

IPC: H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive memory element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer having perpendicular magnetic anisotropy, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. A first surface of the first dielectric is in contact with a first surface of the free magnetic layer. The magnetoresistive memory element further includes a second dielectric, having a first surface that is in contact with a second surface of the free magnetic layer, a conductor, including electrically conductive material, and an electrode, disposed between the second dielectric and the conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion including at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

Abstract translation: 磁阻存储元件（例如，自旋转矩磁阻存储元件）包括固定磁性层，具有垂直磁各向异性的自由磁性层和设置在固定磁性层和自由磁性层之间的第一电介质。 第一电介质的第一表面与自由磁性层的第一表面接触。 磁阻存储元件还包括第二电介质，其具有与自由磁性层的第二表面接触的第一表面，包括导电材料的导体以及设置在第二电介质和导体之间的电极。 电极包括：（i）具有与第二电介质的第二表面接触的表面的非铁磁部分，和（ii）第二部分，其包括设置在第二电介质的非铁磁部分之间的至少一个铁磁材料 电极和导体。

公开(公告)号：US20160099039A1

公开(公告)日：2016-04-07

申请号：US14970563

申请日：2015-12-16

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Matthew R. Croft ,  Chitra Subramanian ,  Halbert Lin

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F11/1048 ,  G06F11/1076 ,  G11C11/00 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0076 ,  G11C2029/0411

Abstract: A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample magnetic bits in the array, apply a write current pulse to the magnetic bits to set them to a first logic state, resample the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. For each of the magnetic bits in the page having the second logic state, the array write circuits initiate a write-back, wherein the write-back includes applying a second write current pulse having opposite polarity in comparison with the first write current pulse to set the magnetic bit to the second state. A read or write operation may be received after initiation of the write-back where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time. An offset current may also be used during resampling.

Abstract translation: 自旋转矩磁阻存储器包括耦合到磁头阵列的阵列读取电路和阵列写入电路。 阵列读取电路对阵列中的磁头进行采样，向磁头施加写入电流脉冲以将其设置为第一逻辑状态，对磁头进行重新采样，并比较采样和重采样的结果，以确定每个磁性的位状态 位。 对于具有第二逻辑状态的页面中的每个磁性位，阵列写入电路启动回写，其中写回包括施加与第一写入电流脉冲相比具有相反极性的第二写入电流脉冲以设置 磁头到第二个状态。 在写回开始之后可以接收读取或写入操作，其中在写入操作的情况下可以中止一部分位的写回。 可以执行回写，使得磁头的不同部分在不同的时间被写回，从而及时地交错回写电流脉冲。 在重采样期间也可以使用偏移电流。

公开(公告)号：US20160093349A1

公开(公告)日：2016-03-31

申请号：US14502367

申请日：2014-09-30

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Dimitri Houssameddine ,  Syed M. Alam ,  Jon Slaughter ,  Chitra Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F12/0804 ,  G11C11/1677 ,  Y02D10/13

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

Abstract translation: 存储器设备被配置为识别要从第一状态改变到第二状态的位单元的集合。 在一些示例中，存储器件可以向该位单元集合施加第一电压以将位组中的至少第一部分改变为第二状态。 在一些情况下，存储器件还可以识别在应用第一电压之后保持在第一状态的位单元的第二部分。 在这些情况下，存储器件可以将具有更大幅度，持续时间或两者的第二电压施加到位单元集合的第二部分，以便将位单元的第二部分设置为第二状态。

公开(公告)号：US20160085622A1

公开(公告)日：2016-03-24

申请号：US14495713

申请日：2014-09-24

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1008 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/104 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/106 ,  G06F11/1068 ,  G06F11/1076 ,  G11C7/1006 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  H03M13/091 ,  H03M13/15 ,  H03M13/19 ,  H03M13/2906 ,  H03M13/43 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0061

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on whether the majority of bits are set to a high state or a low state. For instance, the memory device may be configured to set each bit in the memory array to a low state when the data is read. The memory device may then be configured to store the data in the original state when a majority of the bits to be written to the array are in the low state and in the inverted state when the majority of the bits to be written to the array are in the high state.

Abstract translation: 在一些示例中，存储器件可以被配置为至少部分地基于大多数位是否被设置为高状态还是低状态来存储原始或反相状态的数据。 例如，存储器件可以被配置为当读取数据时将存储器阵列中的每个位设置为低状态。 然后，当要写入阵列的大多数位处于低状态时，存储器件可以被配置为将数据存储在原始状态，当要写入阵列的大部分位是 处于高境界。

公开(公告)号：US09293698B2

公开(公告)日：2016-03-22

申请号：US14701831

申请日：2015-05-01

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jason Janesky ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  B82Y10/00

CPC classification number: H01L43/02 ,  B82Y10/00 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  Y10S977/935

Abstract: In one aspect, the present inventions are directed to a magnetoresistive structure having a tunnel junction, and a process for manufacturing such a structure. The tunnel barrier may be formed between a free layer and a fixed layer in a plurality of repeating process of depositing a metal material and oxidizing at least a portion of the metal material. Where the tunnel barrier is formed by deposition of at least three metal materials interceded by an associated oxidization thereof, the oxidation dose associated with the second metal material may be greater than the oxidation doses associated with the first and third metal materials. In certain embodiments, the fixed layer may include a discontinuous layer of a metal, for example, Ta, in the fixed layer between two layers of a ferromagnetic material.

Abstract translation: 一方面，本发明涉及具有隧道结的磁阻结构，以及制造这种结构的方法。 可以在沉积金属材料和氧化至少一部分金属材料的多个重复工艺中，在自由层和固定层之间形成隧道势垒。 在通过沉积由其相关氧化作用介入的至少三种金属材料形成隧道势垒的地方，与第二金属材料相关的氧化剂量可能大于与第一和第三金属材料相关联的氧化剂量。 在某些实施例中，固定层可以在两层铁磁材料之间的固定层中包括不连续的金属层，例如Ta。