公开(公告)号：US10707206B2

公开(公告)日：2020-07-07

申请号：US16194691

申请日：2018-11-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L27/08 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311

Abstract: A method of forming a gate cut isolation, a related structure and IC are disclosed. The method forms a dummy gate material mandrel having a sidewall positioned between and spaced from a first active region covered by the mandrel and a second active region not covered by the mandrel. A gate cut dielectric layer is formed against the sidewall of the mandrel, and may be trimmed. A dummy gate material may deposited to encase the remaining gate cut dielectric layer. Subsequent dummy gate formation and replacement metal gate processing forms a gate conductor with the gate cut isolation electrically isolating respective first and second portions of the gate conductor. The method creates a very thin, slightly non-vertical gate cut isolation, and eliminates the need to define a gate cut critical dimension or fill a small gate cut opening.

公开(公告)号：US20200211903A1

公开(公告)日：2020-07-02

申请号：US16237757

申请日：2019-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： JIEHUI SHU ,  JESSICA MARY DECHENE ,  HUI ZANG ,  NAVED AHMED SIDDIQUI

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/308

Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to methods of forming a two-part trench in a semiconductor device that includes one or more field-effect transistors (FETs). The present method includes forming a semiconductor layer above a substrate, forming a mask layer above the semiconductor layer, forming a mask opening with sidewalls in the mask layer and exposing the semiconductor layer, depositing a profile control layer on the sidewalls of the mask opening, and forming a trench in the semiconductor layer by simultaneously etching the profile control layer and the exposed semiconductor layer, where the etching of the profile control layer forms the trench with top and bottom sections having different widths.

公开(公告)号：US10700653B2

公开(公告)日：2020-06-30

申请号：US15959514

申请日：2018-04-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Konstantinos Manetakis ,  Thomas G. McKay

IPC: H03F3/04 ,  H03F3/45

Abstract: Methods form amplifier device structures that include first-third amplifier devices. The first amplifier device produces an intermediate signal. The second amplifier device is connected to an input of the first amplifier device and produces an amplified inverted output signal. The third amplifier device inverts the intermediate signal to produce an amplified non-inverted output signal that is complementary to the amplified inverted output signal. A resistor feedback loop is connected to the input and output of the first amplifier device. A gain ratio of the gain of the third amplifier device to the gain of the second amplifier device matches a resistance ratio of the source resistance of the input signal to the resistance of the resistor added to the source resistance. Also, DC loop circuits are connected to the first-third amplifier devices, and each of the DC loop circuits connects an amplifier device output to an amplifier device input.

公开(公告)号：US10699942B2

公开(公告)日：2020-06-30

申请号：US15961337

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Daniel Chanemougame ,  Steven Soss ,  Lars Liebmann ,  Hui Zang ,  Shesh Mani Pandey

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/78

Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

公开(公告)号：US10690845B1

公开(公告)日：2020-06-23

申请号：US16298354

申请日：2019-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Abu Thomas ,  Yusheng Bian

IPC: G02B6/12 ,  G02B6/124 ,  G02B6/136 ,  H01L27/12 ,  G02B6/30

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to three dimensional (3D) optical interconnect structures and methods of manufacture. The structure includes: a first structure having a grating coupler and a first optical waveguide structure; and a second structure having a second optical waveguide structure in alignment with the first optical waveguide structure and which has a modal effective index that matches to the first optical waveguide structure.

公开(公告)号：US10680557B2

公开(公告)日：2020-06-09

申请号：US16367113

申请日：2019-03-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafiullah Syed ,  Abdellatif Bellaouar ,  Chi Zhang

IPC: H03F1/02 ,  H03F3/195 ,  H04B1/04 ,  H03F3/45 ,  H03F3/217 ,  H03F1/14 ,  H01L21/84 ,  H01L27/12

Abstract: An apparatus, comprising an input transformer; a first differential transistor pair configured to receive a first back gate bias voltage; a second differential transistor pair configured to receive a second back gate bias voltage; a cross-coupled neutralization cap comprising PMOS or NMOS transistors and configured to receive a third back gate bias voltage; and an output transformer. A method of fixing at least one back gate bias voltage to impart a desired capacitance to the transistors of at least one of the first differential transistor pair, the second differential transistor pair, or the neutralization cap. The apparatus and method may provide a power amplifier having improved linearity and efficiency.

公开(公告)号：US10680065B2

公开(公告)日：2020-06-09

申请号：US16052140

申请日：2018-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Timothy J. McArdle ,  Jody Fronheiser ,  El Mehdi Bazizi ,  Yi Qi

IPC: H01L29/10 ,  H01L29/08 ,  H01L27/12 ,  H01L29/165 ,  H01L21/84 ,  H01L21/02 ,  H01L21/308 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/027 ,  H01L29/786

Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A channel region is arranged laterally between a first source/drain region and a second source/drain region. The channel region includes a first semiconductor layer and a second semiconductor layer arranged over the first semiconductor layer. A gate structure is arranged over the second semiconductor layer of the channel region The first semiconductor layer is composed of a first semiconductor material having a first carrier mobility. The second semiconductor layer is composed of a second semiconductor material having a second carrier mobility that is greater than the first carrier mobility of the first semiconductor layer.

公开(公告)号：US20200176589A1

公开(公告)日：2020-06-04

申请号：US16207915

申请日：2018-12-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Mark Goldstein

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/265 ,  H01L21/762 ,  C23C16/40 ,  C23C16/48

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. A semiconductor layer is implanted over a first depth range of an inert gas species to modify the crystal structure of a semiconductor material of the semiconductor layer and form a first modified region. The semiconductor layer is annealed with a first annealing process to convert the semiconductor material within the first modified region to a non-single-crystal layer. The semiconductor layer is also implanted with ions of an element over a second depth range to modify the crystal structure of the semiconductor material of the semiconductor layer and form a second modified region containing a concentration of the element. The semiconductor layer is annealed with a second annealing process to convert the semiconductor material within the second modified region to an insulator layer containing the element.

公开(公告)号：US10672439B2

公开(公告)日：2020-06-02

申请号：US16031350

申请日：2018-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dhani Reddy Sreenivasula Reddy ,  Md Nadeem Iqbal

IPC: G11C7/12 ,  G11C7/06 ,  G11C11/4097 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/18

Abstract: The present disclosure relates to a structure which includes at least one keeper circuit which is configured to hold data to a precharged state during a first operation and be disabled during a second operation.

公开(公告)号：US20200168731A1

公开(公告)日：2020-05-28

申请号：US16776807

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chung Foong Tan ,  Guowei Xu ,  Haiting Wang ,  Yue Zhong ,  Ruilong Xie ,  Tek Po Rinus Lee ,  Scott Beasor

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/768 ,  H01L29/08

Abstract: An integrated circuit product is disclosed that includes a transistor device that includes a final gate structure, a gate cap, a low-k sidewall spacer positioned on and in contact with opposing sidewalls of the final gate structure, first and second contact etch stop layers (CESLs) located on opposite sides of the final gate structure, whereby the CESLs are positioned on and in contact with the low-k sidewall spacer, and a high-k spacer located on opposite sides of the final gate structure, wherein the high-k spacer is positioned in recesses formed in an upper portion of the CESLs.