公开(公告)号：US06214648B1

公开(公告)日：2001-04-10

申请号：US09604762

申请日：2000-06-26

Applicant: Myeong Jin Shin

Inventor： Myeong Jin Shin

IPC: H01L2144

CPC classification number: H01L23/24 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1058 ,  H01L2924/1627 ,  H01L2924/00014

Abstract: The semiconductor chip package includes a package body with a recess and a plurality of barrier parts formed along one side thereof. Each of the barrier parts has a first region and a second region projecting from the first region, and adjacent first regions are separated by a slot. A semiconductor chip, including a reference surface having a circuit and a plurality of bonding pads formed thereon, is disposed in the recess of the package body. A conductive member is disposed in each slot, and a connecting member, associated with each bonding pad, electrically connects the associated bonding pad with a corresponding conductive member. A sealing member seals the semiconductor chip, the connecting members, and at least a portion of the conductive members in contact with the connecting members. Stacking these packages in the transverse and/or longitudinal direction further reduces their mounting area and increases the integrated capacity per unit of mounting area.

Abstract translation: 半导体芯片封装包括具有凹部的封装主体和沿其一侧形成的多个阻挡部。 每个阻挡部分具有从第一区域突出的第一区域和第二区域，并且相邻的第一区域被槽间隔开。 包括具有电路的参考表面和形成在其上的多个接合焊盘的半导体芯片设置在封装体的凹部中。 导电构件设置在每个槽中，并且与每个接合焊盘相关联的连接构件将相关联的焊盘与相应的导电构件电连接。 密封构件密封半导体芯片，连接构件以及与连接构件接触的至少一部分导电构件。 在横向和/或纵向上堆叠这些包装件进一步减小了它们的安装面积并且增加了每单位安装面积的集成容量。

公开(公告)号：US06204125B1

公开(公告)日：2001-03-20

申请号：US09605632

申请日：2000-06-28

Applicant: Keun Woo Lee ,  Ki Seog Kim ,  Jin Shin ,  Sung Kee Park

Inventor： Keun Woo Lee ,  Ki Seog Kim ,  Jin Shin ,  Sung Kee Park

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L21/28273

Abstract: The present invention relates to a method of forming a gate in a stack gate flash EEPROM cell. In order to preventing a lateral bird's beak from occurring in an ONO dielectric layer during a reoxidation process to be performed after a formation of a cell gate having a stack structure formed by stacking a floating gate, an ONO dielectric layer and a control gate, an oxide layer and a nitride layer are sequentially formed on an entire structure before the reoxidation and after a formation of the cell gate. The oxide layer serves to reduce a stress in depositing the nitride layer, and the nitride layer serves to prevent an occurrence of the lateral bird's beak of the ONO dielectric layer during the reoxidation process. Accordingly, the present invention prevents the lateral bird's beak of the ONO dielectric layer, thereby improving a speed of cell erase operation.

Abstract translation: 本发明涉及一种在堆叠栅极快闪EEPROM单元中形成栅极的方法。 为了防止在形成具有通过堆叠浮栅，ONO电介质层和控制栅形成的堆叠结构的电池栅极的再氧化工艺期间在ONO电介质层中发生侧面鸟嘴， 氧化层和氮化物层在再氧化之前和电池栅极形成之后的整个结构上依次形成。 氧化物层用于减少沉积氮化物层的应力，并且氮化物层用于在再氧化过程期间防止ONO电介质层的侧面鸟喙的发生。 因此，本发明能够防止ONO电介质层的横向鸟嘴，从而提高电池擦除操作的速度。

公开(公告)号：US6140700A

公开(公告)日：2000-10-31

申请号：US966703

申请日：1997-11-10

Applicant: Myeong Jin Shin

Inventor： Myeong Jin Shin

IPC: H01L21/60 ,  H01L23/00 ,  H01L23/04 ,  H01L23/24 ,  H01L23/28 ,  H01L25/10

CPC classification number: H01L23/24 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1058 ,  H01L2924/1627

Abstract: The semiconductor chip package includes a package body with a recess and a plurality of barrier parts formed along one side thereof. Each of the barrier parts has a first region and a second region projecting from the first region, and adjacent first regions are separated by a slot. A semiconductor chip, including a reference surface having a circuit and a plurality of bonding pads formed thereon, is disposed in the recess of the package body. A conductive member is disposed in each slot, and a connecting member, associated with each bonding pad, electrically connects the associated bonding pad with a corresponding conductive member. A sealing member seals the semiconductor chip, the connecting members, and at least a portion of the conductive members in contact with the connecting members. Stacking these packages in the transverse and/or longitudinal direction further reduces their mounting area and increases the integrated capacity per unit of mounting area.

Abstract translation: 半导体芯片封装包括具有凹部的封装主体和沿其一侧形成的多个阻挡部。 每个阻挡部分具有从第一区域突出的第一区域和第二区域，并且相邻的第一区域被槽间隔开。 包括具有电路的参考表面和形成在其上的多个接合焊盘的半导体芯片设置在封装体的凹部中。 导电构件设置在每个槽中，并且与每个接合焊盘相关联的连接构件将相关联的焊盘与相应的导电构件电连接。 密封构件密封半导体芯片，连接构件以及与连接构件接触的至少一部分导电构件。 在横向和/或纵向上堆叠这些包装件进一步减小了它们的安装面积并且增加了每单位安装面积的集成容量。

公开(公告)号：US5682887A

公开(公告)日：1997-11-04

申请号：US618880

申请日：1996-03-20

Applicant: Beilei Xu ,  Jin-Shin Chou ,  Jianzhong Qian

Inventor： Beilei Xu ,  Jin-Shin Chou ,  Jianzhong Qian

IPC: G06T7/20 ,  G06T7/60 ,  A61B5/00

CPC classification number: G06T7/60 ,  G06T7/20

Abstract: This invention provides a method for determining the position range of the heart from a sequence of projection images which are acquired for 3-D volume reconstruction, such as SPECT myocardial projection data. The essence of this invention is the use of 1-D pseudo motion analysis so that the detection is insensitive to the image intensity distribution. Heart position is determined by comparing the sampled heart motion against a standard heart motion and determining similarities between the two as an indication of the position range of the sampled heart including the proximate center, upper and lower limits of motion.

Abstract translation: 本发明提供了一种用于根据用于3-D体积重建获取的投影图像序列（例如SPECT心肌投影数据）来确定心脏的位置范围的方法。 本发明的实质是使用1-D伪运动分析，使得检测对图像强度分布不敏感。 通过将采样的心脏运动与标准心脏运动进行比较来确定心脏位置，并且确定两者之间的相似性作为包括接近中心运动的上限和下限的采样心脏的位置范围的指示。

公开(公告)号：US5594719A

公开(公告)日：1997-01-14

申请号：US350019

申请日：1994-11-29

Applicant: Don-Sung Oh ,  Dong-Jin Shin

Inventor： Don-Sung Oh ,  Dong-Jin Shin

IPC: H04B3/23 ,  H04M3/00 ,  H04Q3/545 ,  H04J3/00

CPC classification number: H04Q3/54516 ,  H04B3/23 ,  H04M3/002

Abstract: The invention is a method for controlling an echo canceller circuit including a data storage for storing a program for processing digital signals to cancel an echo in PCM encoded voice data, a plurality of digital signal processors each having a reset terminal and which are downloaded with the program which is executed by the plurality of digital signal processor to carry out removal of the echo in the PCM encoded voice data, and a one chip controller for performing control functions of the echo canceller. The method comprises the steps after completion of initialization of the one chip controller, controlling the reset terminals of the digital signal processors to maintain all of the digital signal processors in reset state; releasing one digital signal processor from the reset state and downloading the program to the one released digital signal processor from the data storage; and the released one digital signal processor processing the PCM encoded voice data with the program to remove the echo from the PCM encoded voice data.

Abstract translation: 本发明是一种用于控制回波消除电路的方法，包括：数据存储器，用于存储用于处理数字信号的程序，以消除PCM编码语音数据中的回波;多个数字信号处理器，每个数字信号处理器具有复位终端， 由多个数字信号处理器执行以执行PCM编码语音数据中的回波的程序，以及用于执行回波消除器的控制功能的单片控制器。 该方法包括完成单片机控制器初始化之后的步骤，控制数字信号处理器的复位端，使所有数字信号处理器保持复位状态; 从复位状态释放一个数字信号处理器，并从该数据存储器将该程序下载到一个已释放的数字信号处理器; 并且释放的一个数字信号处理器利用程序处理PCM编码的语音数据以从PCM编码的语音数据中去除回声。

公开(公告)号：US09818908B2

公开(公告)日：2017-11-14

申请号：US14123638

申请日：2012-05-25

Applicant: Hyung Jin Shin ,  Gi Won Hong ,  Young Dae Baek

Inventor： Hyung Jin Shin ,  Gi Won Hong ,  Young Dae Baek

IPC: H01L33/00 ,  H01L21/56 ,  H01L23/00 ,  H01L33/54 ,  H01L33/58 ,  H01L21/67

CPC classification number: H01L33/005 ,  H01L21/56 ,  H01L21/565 ,  H01L21/67126 ,  H01L24/97 ,  H01L33/0095 ,  H01L33/54 ,  H01L33/58 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2933/005 ,  H01L2933/0058 ,  H01L2924/00

Abstract: Disclosed is an apparatus for forming an encapsulation material for a light emitting device. The apparatus for forming an encapsulation material comprises: an upper mold on which is mounted a substrate having a plurality of optical semiconductors; a lower mold arranged opposite the upper mold; a resin-capture space for capturing a resin between the upper mold and the lower mold; and an ejector pin for dividing the resin-capture space into a plurality of spaces at the position where the encapsulating material is formed, thereby dividing the encapsulation material into a plurality of parts formed on the substrate.

公开(公告)号：US20170077136A1

公开(公告)日：2017-03-16

申请号：US15218610

申请日：2016-07-25

Applicant: Jung Ho KIM ,  BiO KIM ,  Hyung Joon KIM ,  Young Seon SON ,  Su Jin SHIN ,  Jae Young AHN ,  Ju Mi YUN ,  HanMei CHOI

Inventor： Jung Ho KIM ,  BiO KIM ,  Hyung Joon KIM ,  Young Seon SON ,  Su Jin SHIN ,  Jae Young AHN ,  Ju Mi YUN ,  HanMei CHOI

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/7926

Abstract: A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.

Abstract translation: 半导体器件包括垂直堆叠在衬底上的栅极电极和通过栅电极的通道孔，以垂直于衬底延伸，并且包括栅介质层和沟道区。 栅极电介质层可以由多个层形成，并且多个层中的至少一层可以在不同位置具有不同的厚度。

公开(公告)号：US09576916B2

公开(公告)日：2017-02-21

申请号：US13543050

申请日：2012-07-06

Applicant: Hyeon-jin Shin ,  Jae-young Choi ,  Seong-chan Jun ,  Whan-kyun Kim ,  Hyung-seo Yoon ,  Ju-yeong Oh ,  Ju-hwan Lim

Inventor： Hyeon-jin Shin ,  Jae-young Choi ,  Seong-chan Jun ,  Whan-kyun Kim ,  Hyung-seo Yoon ,  Ju-yeong Oh ,  Ju-hwan Lim

IPC: H01L23/66 ,  H01L23/532 ,  H01L27/04

CPC classification number: H01L23/66 ,  H01L23/53276 ,  H01L27/04 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high frequency circuit includes a first electronic device, a second electronic device, and a graphene interconnection unit, where at least one of a trench and a via is defined under the graphene interconnection unit.

Abstract translation: 高频电路包括第一电子器件，第二电子器件和石墨烯互连单元，其中沟槽和通孔中的至少一个限定在石墨烯互连单元下方。

公开(公告)号：US20160343729A1

公开(公告)日：2016-11-24

申请号：US15142365

申请日：2016-04-29

Applicant: Hyun-Jin SHIN ,  Hong-Suk KIM ,  Jung-Hwan KIM ,  Sang-Hoon LEE ,  Hun-Hyeong LIM ,  Yong-Seok CHO ,  Young-Dae KIM ,  Han-Vit YANG

Inventor： Hyun-Jin SHIN ,  Hong-Suk KIM ,  Jung-Hwan KIM ,  Sang-Hoon LEE ,  Hun-Hyeong LIM ,  Yong-Seok CHO ,  Young-Dae KIM ,  Han-Vit YANG

IPC: H01L27/115 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/0206 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/76826 ,  H01L21/76831 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of manufacturing a semiconductor device, the method including forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed; forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and deoxidizing the metal oxide layer so that the preliminary buffer oxide layer is transformed into a buffer oxide layer.

Abstract translation: 一种制造半导体器件的方法，所述方法包括在衬底上形成结构，所述结构包括金属图案，所述金属图案的至少一部分被暴露; 形成预备的缓冲氧化物层以覆盖该结构，金属氧化物层形成在金属图案的暴露部分; 并且使金属氧化物层脱氧，使得预备缓冲氧化物层转变成缓冲氧化物层。

公开(公告)号：US20160133643A1

公开(公告)日：2016-05-12

申请号：US14995586

申请日：2016-01-14

Applicant: Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

Inventor： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28008 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/7926

Abstract: A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.

Abstract translation: 提供半导体器件。 半导体包括在基板上沿第一方向交替堆叠的多个层间绝缘层和多个栅电极。 多个层间绝缘层和多个栅电极构成在第一方向上延伸的侧面。 栅电介质层设置在侧表面上。 沟道图案设置在栅介质层上。 栅介质层包括保护图案，电荷陷阱层和隧穿层。 保护图案包括设置在多个栅电极的对应的栅电极上的部分。 电荷陷阱层设置在保护图案上。 隧道层设置在电荷陷阱层和沟道图案之间。 保护图案比电荷陷阱层更致密。