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    Coherency directory entry allocation based on eviction costs
    71.
    发明授权
    Coherency directory entry allocation based on eviction costs 有权

    公开(公告)号：US10705958B2

    公开(公告)日：2020-07-07

    申请号：US16108696

    申请日：2018-08-22

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Michael W. Boyer ,  Gabriel H. Loh ,  Yasuko Eckert ,  William L. Walker

    IPC: G06F12/12 ,  G06F12/0817 ,  G06F12/0842 ,  G06F11/30

    Abstract: A processor partitions a coherency directory into different regions for different processor cores and manages the number of entries allocated to each region based at least in part on monitored recall costs indicating expected resource costs for reallocating entries. Examples of monitored recall costs include a number of cache evictions associated with entry reallocation, the hit rate of each region of the coherency directory, and the like, or a combination thereof. By managing the entries allocated to each region based on the monitored recall costs, the processor ensures that processor cores associated with denser memory access patterns (that is, memory access patterns that more frequently access cache lines associated with the same memory pages) are assigned more entries of the coherency directory.

    Hybrid cache
    73.
    发明授权
    Hybrid cache 有权

    公开(公告)号：US10255190B2

    公开(公告)日：2019-04-09

    申请号：US14973448

    申请日：2015-12-17

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gabriel H. Loh

    IPC: G06F12/08 ,  G06F17/40 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0846

    Abstract: Systems, apparatuses, and methods for implementing a hybrid cache. A processor may include a hybrid L2/L3 cache which allows the processor to dynamically adjust a size of the L2 cache and a size of the L3 cache. In some embodiments, the processor may be a multi-core processor and there may be a single cache partitioned into a logical L2 cache and a logical L3 cache for use by the cores. In one embodiment, the processor may track the cache hit rates of the logical L2 and L3 caches and adjust the sizes of the logical L2 and L3 cache based on the cache hit rates. In another embodiment, the processor may adjust the sizes of the logical L2 and L3 caches based on which application is currently being executed by the processor.

    Page migration in a 3D stacked hybrid memory
    78.
    发明授权
    Page migration in a 3D stacked hybrid memory 有权
    3D堆叠混合内存中的页面迁移

    公开(公告)号：US09535831B2

    公开(公告)日：2017-01-03

    申请号：US14152003

    申请日：2014-01-10

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Nuwan S. Jayasena ,  Gabriel H. Loh ,  James M. O'Connor ,  Niladrish Chatterjee

    IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06 ,  G06F12/08 ,  G11C11/00 ,  G06F12/06

    CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/205 ,  G11C11/005 ,  Y02D10/13

    Abstract: A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more memory dies, the set of one or more logic dies comprising a memory interface and a page migration manager, the memory interface coupleable to a device external to the die-stacked hybrid memory device, and the page migration manager to transfer memory pages between the first set of one or more memory dies and the second set of one or more memory dies.

    Abstract translation: 芯片堆叠的混合存储器设备实现实现第一存储器架构类型的第一存储器单元电路的一个或多个存储器管芯的第一组和执行第二存储器架构类型不同的第二存储器单元电路的一个或多个存储器管芯的第二组 比第一个内存架构类型。 芯片堆叠式混合存储器件还包括电耦合到一个或多个存储器管芯的第一和第二组的一个或多个逻辑管芯组，该组一个或多个逻辑管芯包括存储器接口和页迁移管理器， 所述存储器接口可耦合到所述管芯堆叠式混合存储器件外部的器件，以及所述页面迁移管理器，用于在所述第一组一个或多个存储器管芯与所述第二组一个或多个存储器管芯之间传送存储器页。

    Partitionable data bus
    79.
    发明授权
    Partitionable data bus 有权
    可分区数据总线

    公开(公告)号：US09454419B2

    公开(公告)日：2016-09-27

    申请号：US14016610

    申请日：2013-09-03

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gabriel H. Loh ,  Yi Xu ,  James M. O'Connor

    IPC: G06F11/00 ,  G06F11/07 ,  G06F11/20

    CPC classification number: G06F11/0727 ,  G06F11/2007 ,  G06F2201/85

    Abstract: A method and a system are provided for partitioning a system data bus. The method can include partitioning off a portion of a system data bus that includes one or more faulty bits to form a partitioned data bus. Further, the method includes transferring data over the partitioned data bus to compensate for data loss due to the one or more faulty bits in the system data bus.

    Abstract translation: 提供了一种分区系统数据总线的方法和系统。 该方法可以包括分离包括一个或多个故障位的系统数据总线的一部分以形成分区数据总线。 此外，该方法包括在分区数据总线上传送数据以补偿由于系统数据总线中的一个或多个错误位导致的数据丢失。

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