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    BALANCING COMPUTATION AND COMMUNICATION POWER IN POWER CONSTRAINED CLUSTERS
    72.
    发明申请
    BALANCING COMPUTATION AND COMMUNICATION POWER IN POWER CONSTRAINED CLUSTERS 有权

    公开(公告)号：US20170160781A1

    公开(公告)日：2017-06-08

    申请号：US14959669

    申请日：2015-12-04

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Leonardo Piga ,  Indrani Paul ,  Wei Huang

    IPC: G06F1/32

    CPC classification number: G06F1/3203 ,  G06F1/3206 ,  G06F1/3287 ,  Y02D10/171

    Abstract: Systems, apparatuses, and methods for balancing computation and communication power in power constrained environments. A data processing cluster with a plurality of compute nodes may perform parallel processing of a workload in a power constrained environment. Nodes that finish tasks early may be power-gated based on one or more conditions. In some scenarios, a node may predict a wait duration and go into a reduced power consumption state if the wait duration is predicted to be greater than a threshold. The power saved by power-gating one or more nodes may be reassigned for use by other nodes. A cluster agent may be configured to reassign the unused power to the active nodes to expedite workload processing.

    SYSTEM AND METHOD FOR DETERMINING CONCURRENCY FACTORS FOR DISPATCH SIZE OF PARALLEL PROCESSOR KERNELS
    73.
    发明申请
    SYSTEM AND METHOD FOR DETERMINING CONCURRENCY FACTORS FOR DISPATCH SIZE OF PARALLEL PROCESSOR KERNELS 有权
    用于确定并行处理器卡尺的分配因子的系数和方法

    公开(公告)号：US20160335143A1

    公开(公告)日：2016-11-17

    申请号：US14710879

    申请日：2015-05-13

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Rathijit Sen ,  Indrani Paul ,  Wei Huang

    IPC: G06F9/54 ,  G06F9/445

    CPC classification number: G06F9/545 ,  G06F9/44505 ,  Y02D10/43

    Abstract: Disclosed is a method of determining concurrency factors for an application running on a parallel processor. Also disclosed is a system for implementing the method. In an embodiment, the method includes running at least a portion of the kernel as sequences of mini-kernels, each mini-kernel including a number of concurrently executing workgroups. The number of concurrently executing workgroups is defined as a concurrency factor of the mini-kernel. A performance measure is determined for each sequence of mini-kernels. From the sequences, a particular sequence is chosen that achieves a desired performance of the kernel, based on the performance measures. The kernel is executed with the particular sequence.

    Abstract translation: 公开了一种确定并行处理器上运行的应用程序的并发因子的方法。 还公开了一种用于实现该方法的系统。 在一个实施例中，该方法包括将内核的至少一部分作为小型内核的序列运行，每个小型内核包括多个并发执行的工作组。 并发执行工作组的数量被定义为小型内核的并发因子。 针对每个小型内核序列确定性能指标。 从序列中，基于性能测量，选择实现内核所需性能的特定序列。 内核以特定顺序执行。

    HARDWARE AND RUNTIME COORDINATED LOAD BALANCING FOR PARALLEL APPLICATIONS
    75.
    发明申请
    HARDWARE AND RUNTIME COORDINATED LOAD BALANCING FOR PARALLEL APPLICATIONS 有权
    硬件和运行协调负载均衡并行应用

    公开(公告)号：US20160259667A1

    公开(公告)日：2016-09-08

    申请号：US14641220

    申请日：2015-03-06

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Peter Bailey ,  Indrani Paul ,  Manish Arora

    IPC: G06F9/50

    CPC classification number: G06F9/505 ,  G06F1/3243 ,  G06F1/329 ,  G06F8/443 ,  G06F9/30065 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/4893 ,  G06F9/5094 ,  G06F9/522 ,  G06F2209/5019 ,  Y02D10/152 ,  Y02D10/24

    Abstract: A method of balancing execution rates for a plurality of parallel program loops being executed concurrently by a processor may include estimating a completion time for each program loop of the plurality of program loops, determining a difference between the estimated completion time of a first program loop of the plurality of program loops and the estimated completion time of a second program loop of the plurality of program loops, and decreasing the difference by adjusting an execution rate of the first program loop.

    Abstract translation: 一种平衡处理器并行执行的多个并行程序循环的执行率的方法可以包括：估计多个程序循环中每个程序循环的完成时间，确定第一程序循环的估计完成时间之间的差异 所述多个程序循环的多个程序循环和所述多个程序循环的第二程序循环的估计完成时间，以及通过调整所述第一程序循环的执行速率来减小所述差异。

    DECOUPLED ENTRY AND EXIT PREDICTION FOR POWER GATING
    78.
    发明申请
    DECOUPLED ENTRY AND EXIT PREDICTION FOR POWER GATING 有权
    放弃进入和退出预测功率增益

    公开(公告)号：US20150370311A1

    公开(公告)日：2015-12-24

    申请号：US14310908

    申请日：2014-06-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Yasuko Eckert ,  Manish Arora ,  Indrani Paul

    IPC: G06F1/32 ,  G06N5/04

    CPC classification number: G06F1/3296 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/3293 ,  G06N5/04 ,  Y02D10/171 ,  Y02D50/20

    Abstract: Power gating logic detects a transition of a component of a processing device into an idle state. In response to detecting the transition, the entry/exit power gating logic selectively implements one or more entry prediction techniques for power gating the component based on estimates of reliability of the entry prediction techniques. The entry/exit power gating logic also selectively implements one or more exit prediction techniques for exiting the power gated state based on estimates of reliability of the exit prediction techniques.

    Abstract translation: 电源门控逻辑检测处理设备的组件转换到空闲状态。 响应于检测到转换，入口/出口功率门控逻辑基于入口预测技术的可靠性的估计，选择性地实现用于功率门控组件的一个或多个入口预测技术。 入口/出口电力门控逻辑还基于对退出预测技术的可靠性的估计，选择性地实现一个或多个退出预测技术以退出电力门控状态。

    POWER MANAGEMENT ACROSS HETEROGENEOUS PROCESSING UNITS
    79.
    发明申请
    POWER MANAGEMENT ACROSS HETEROGENEOUS PROCESSING UNITS 有权
    电源管理异步加工单元

    公开(公告)号：US20150355692A1

    公开(公告)日：2015-12-10

    申请号：US14297208

    申请日：2014-06-05

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Indrani Paul ,  Vignesh Trichy Ravi ,  Manish Arora ,  Srilatha Manne

    IPC: G06F1/20 ,  G06F9/50 ,  G06F11/30 ,  G06F1/32

    CPC classification number: G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F9/5094 ,  G06F11/3058 ,  G06F11/3409 ,  G06F11/3447 ,  Y02D10/126 ,  Y02D10/22

    Abstract: A method includes controlling active frequency states of a plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. A processor includes a plurality of heterogeneous processing units and a performance controller to control active frequency states of the plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. The active frequency state of a first type of processing unit in the plurality of heterogeneous processing units is controlled based on a first activity metric associated with a first type of processing unit and a second activity metric associated with a second type of processing unit.

    Abstract translation: 一种方法包括基于指示多个异构处理单元中的不同类型的处理单元之间的性能耦合的频率灵敏度度量来控制多个异构处理单元的活动频率状态。 处理器包括多个异构处理单元和性能控制器，用于基于指示多个异构处理单元中的不同类型的处理单元之间的性能耦合的频率灵敏度度量来控制多个异构处理单元的有效频率状态。 基于与第一类型处理单元相关联的第一活动度量和与第二类型处理单元相关联的第二活动度量来控制多个异构处理单元中的第一类型处理单元的活动频率状态。

    CONFIGURING PROCESSOR POLICIES BASED ON PREDICTED DURATIONS OF ACTIVE PERFORMANCE STATES
    80.
    发明申请
    CONFIGURING PROCESSOR POLICIES BASED ON PREDICTED DURATIONS OF ACTIVE PERFORMANCE STATES 审中-公开
    基于预期活跃绩效状态的配置处理者政策

    公开(公告)号：US20150186160A1

    公开(公告)日：2015-07-02

    申请号：US14146588

    申请日：2014-01-02

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan S. Jayasena ,  Srilatha Manne

    IPC: G06F9/445 ,  G06F11/34 ,  G06F12/08

    CPC classification number: G06F11/3423 ,  G06F1/3243 ,  G06F11/3452 ,  G06F12/0804 ,  G06F12/0864 ,  G06F2212/601 ,  Y02D10/152 ,  Y02D10/34 ,  Y02D50/20

    Abstract: Durations of active performance states of components of a processing system can be predicted based on one or more previous durations of an active state of the components. One or more entities in the processing system such as processor cores or caches can be configured based on the predicted durations of the active state of the components. Some embodiments configure a first component in a processing system based on a predicted duration of an active state of a second component of the processing system. The predicted duration is predicted based on one or more previous durations of an active state of the second component.

    Abstract translation: 可以基于组件的活动状态的一个或多个先前持续时间来预测处理系统的组件的主动性能状态的持续时间。 可以基于组件的活动状态的预测持续时间来配置处理系统中的一个或多个实体，例如处理器核心或高速缓存。 一些实施例基于处理系统的第二组件的活动状态的预测持续时间来配置处理系统中的第一组件。 基于第二组件的活动状态的一个或多个先前持续时间预测预测持续时间。

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