公开(公告)号：US20080242037A1

公开(公告)日：2008-10-02

申请号：US11729189

申请日：2007-03-28

申请人： Bernhard Sell ,  Tahir Ghani ,  Anand Murthy ,  Harry Gomez

发明人： Bernhard Sell ,  Tahir Ghani ,  Anand Murthy ,  Harry Gomez

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

摘要： A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.

摘要翻译： 一种形成具有在晶体管的栅介质层附近的具有自对准源极和漏极延伸部分的晶体管的方法包括在衬底上形成栅极堆叠，将掺杂剂注入到与栅极堆叠相邻的衬底区域中，其中 掺杂剂增加了衬底的蚀刻速率并且限定了源极和漏极延伸部分的位置，在栅堆叠的横向相对侧上形成一对间隔物，该衬垫设置在衬底的掺杂区域的顶部，蚀刻衬底的掺杂区域 以及所述衬底的与所述掺杂区域相邻的部分，其中所述掺杂区域的蚀刻速率高于所述衬底的与所述掺杂区域相邻的部分的蚀刻速率，以及在所述掺杂区域的蚀刻部分中沉积硅基材料 基质。

公开(公告)号：US20050014351A1

公开(公告)日：2005-01-20

申请号：US10918818

申请日：2004-08-12

申请人： Cory Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul Packan ,  Scott Thompson

发明人： Cory Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul Packan ,  Scott Thompson

IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/425

CPC分类号： H01L21/26506 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7842

摘要： Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

摘要翻译： 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

公开(公告)号：US6121100A

公开(公告)日：2000-09-19

申请号：US1337

申请日：1997-12-31

申请人： Ebrahim Andideh ,  Lawrence Brigham ,  Robert S. Chau ,  Tahir Ghani ,  Chia-Hong Jan ,  Justin Sandford ,  Mitchell C. Taylor

发明人： Ebrahim Andideh ,  Lawrence Brigham ,  Robert S. Chau ,  Tahir Ghani ,  Chia-Hong Jan ,  Justin Sandford ,  Mitchell C. Taylor

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/6653 ,  H01L21/2254 ,  H01L21/823814 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/665 ,  H01L29/66545

摘要： A method of forming a MOS transistor. According to the method of the present invention, a pair of source/drain contact regions are formed on opposite sides of a gate electrode. After forming the pair of source/drain contact regions, semiconductor material is deposited onto opposite sides of the gate electrode. Dopants are then diffused from the semiconductor material into the substrate beneath the gate electrode to form a pair of source/drain extensions.

摘要翻译： 一种形成MOS晶体管的方法。 根据本发明的方法，在栅电极的相对侧上形成一对源极/漏极接触区域。 在形成一对源极/漏极接触区域之后，半导体材料沉积在栅电极的相对侧上。 掺杂剂然后从半导体材料扩散到栅电极下方的衬底中，以形成一对源/漏扩展。

公开(公告)号：US09876016B2

公开(公告)日：2018-01-23

申请号：US13996523

申请日：2011-12-30

申请人： Joseph Steigerwald ,  Tahir Ghani ,  Oleg Golonzka

发明人： Joseph Steigerwald ,  Tahir Ghani ,  Oleg Golonzka

IPC分类号： H01L27/092 ,  H01L29/417 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L23/485

CPC分类号： H01L27/0924 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.

公开(公告)号：US09607987B2

公开(公告)日：2017-03-28

申请号：US13996468

申请日：2011-12-21

申请人： Martin D. Giles ,  Tahir Ghani

发明人： Martin D. Giles ,  Tahir Ghani

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L27/1211 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785

摘要： Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.

公开(公告)号：US09490364B2

公开(公告)日：2016-11-08

申请号：US12655329

申请日：2009-12-29

申请人： Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

发明人： Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/161 ,  H01L29/165 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

公开(公告)号：US09196704B2

公开(公告)日：2015-11-24

申请号：US13976831

申请日：2011-12-19

申请人： Jacob Jensen ,  Tahir Ghani ,  Mark Y. Liu ,  Harold Kennel ,  Robert James

发明人： Jacob Jensen ,  Tahir Ghani ,  Mark Y. Liu ,  Harold Kennel ,  Robert James

IPC分类号： H01L21/768 ,  H01L29/66 ,  H01L21/268

CPC分类号： H01L29/66477 ,  H01L21/268 ,  H01L21/76805 ,  H01L21/76883 ,  H01L29/66628

摘要： Laser anneal to melt regions of a microelectronic device buried under overlying materials, such as an interlayer dielectric (ILD). Melting temperature differentiation is employed to selectively melt a buried region. In embodiments a buried region is at least one of a gate electrode and a source/drain region. Laser anneal may be performed after contact formation with contact metal coupling energy into the buried layer for the anneal.

摘要翻译： 激光退火以熔化掩埋在覆盖材料（例如层间电介质（ILD））下的微电子器件的区域。 使用熔融温度分化来选择性地熔化掩埋区域。 在实施例中，掩埋区域是栅极电极和源极/漏极区域中的至少一个。 可以在与接触金属耦合能量接触形成到用于退火的掩埋层中之后执行激光退火。

公开(公告)号：US09166004B2

公开(公告)日：2015-10-20

申请号：US12978359

申请日：2010-12-23

申请人： Michael G. Haverty ,  Sadasivan Shankar ,  Tahir Ghani

发明人： Michael G. Haverty ,  Sadasivan Shankar ,  Tahir Ghani ,  Seongjun Park

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44 ,  H01L29/08 ,  H01L23/485 ,  H01L29/45 ,  H01L23/482 ,  H01L21/283

CPC分类号： H01L29/41791 ,  H01L21/283 ,  H01L21/3205 ,  H01L23/482 ,  H01L23/485 ,  H01L29/0895 ,  H01L29/456 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.

摘要翻译： 公开了用于在硅半导体器件中形成接触的技术。 在一些实施例中，过渡层与硅半导体接触表面形成非反应性界面。 在一些这种情况下，导电材料提供触点和与硅表面形成非反应性界面的材料。 在其他情况下，薄的半导体或绝缘层提供与硅表面的非反应性界面并且耦合到触点的导电材料。 这些技术可以例如在平面或非平面（例如，双栅极和三栅极FinFET））晶体管器件中实现。

公开(公告)号：US09093513B2

公开(公告)日：2015-07-28

申请号：US13786372

申请日：2013-03-05

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L21/336 ,  H01L21/28 ,  H01L21/463 ,  H01L29/78 ,  H01L21/768 ,  H01L29/51 ,  H01L29/49

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20150060945A1

公开(公告)日：2015-03-05

申请号：US14535387

申请日：2014-11-07

申请人： Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Jack T. Kavalieros ,  Roza Kotlyar ,  Willy Rachmady ,  Mark Y. Liu

发明人： Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Jack T. Kavalieros ,  Roza Kotlyar ,  Willy Rachmady ,  Mark Y. Liu

IPC分类号： H01L29/36 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/08

CPC分类号： H01L29/0676 ,  H01L21/02532 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/3215 ,  H01L21/76831 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66931 ,  H01L29/7785 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

摘要翻译： 公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。 在一些实施例中，使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。 在一些这样的情况下，锗浓度可以例如超过50原子％且高达100原子％，并且硼浓度可以例如超过1E20cm-3。 可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。 锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。 这些技术可以例如在平面或非平面晶体管器件中实现。