公开(公告)号：US20080246069A1

公开(公告)日：2008-10-09

申请号：US10597432

申请日：2004-01-30

申请人： Thomas W. Dyer ,  Carl Radens

发明人： Thomas W. Dyer ,  Carl Radens

IPC分类号： H01L29/94 ,  H01L21/20

CPC分类号： H01L28/87 ,  H01L27/1087 ,  H01L29/66181

摘要： A trench capacitor is filled with a set of two or more storage plates by consecutively depositing layers of dielectric and conductor and making contact to the ground plates by etching an aperture through the plates to the buried plate in the substrate and connecting the one or more ground plate to the substrate; the charge storage plates are connected at the top of the capacitor by blocking the end of the first plate during the formation of the second ground plate and exposing the material of the first storage plate during deposition of the second storage plate.

摘要翻译： 通过连续沉积电介质和导体层并且通过将穿过板的孔蚀刻到衬底中的掩埋板并且连接一个或多个接地而与接地板接触而将沟槽电容器填充一组两个或更多个存储板 板到基板; 电荷存储板通过在形成第二接地板期间阻挡第一板的端部并且在第二存储板的沉积期间暴露第一存储板的材料而在电容器的顶部连接。

公开(公告)号：US20080243972A1

公开(公告)日：2008-10-02

申请号：US11694183

申请日：2007-03-30

申请人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L.C. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L.C. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： G06F15/02

CPC分类号： G11C19/0841 ,  B82Y10/00 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1675 ,  Y10T29/53165

摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.

摘要翻译： 具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于 域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括单个写入线，所述单个写入线的纵轴基本上与所述共面移位寄存器结构中的每一个的纵向轴线正交。

公开(公告)号：US20080160752A1

公开(公告)日：2008-07-03

申请号：US11619384

申请日：2007-01-03

申请人： Lawrence Clevenger ,  Timothy J. Dalton ,  Mukta Ghate Farooq ,  William Francis Landers ,  Carl Radens ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy J. Dalton ,  Mukta Ghate Farooq ,  William Francis Landers ,  Carl Radens ,  Chih-Chao Yang

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/11428 ,  H01L2224/1145 ,  H01L2224/1147 ,  H01L2224/11616 ,  H01L2224/1184 ,  H01L2224/11901 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0103 ,  H01L2224/05099

摘要： A damascene method of forming a C4 element includes forming a last level metal layer on a substrate, forming a TV ILD layer on the last level metal layer, forming a lithographically patterned UBM adhesion layer including one of Ti, TiW, Cr and Cu, forming a mandrel layer over the UBM adhesion layer, lithographically patterning the mandrel layer to form an aperture, depositing a solder layer by one of sputtering, evaporation, physical vapor deposition, solder wave or injection molding in the aperture, planarizing the solder layer by CMP, removing the mandrel layer, reflowing the solder to ball the solder to form a ball interconnect, and joining a second substrate with an I/O pad to the ball interconnect.

摘要翻译： 形成C4元件的镶嵌方法包括在基底上形成最后一层金属层，在最后一层金属层上形成TV ILD层，形成包括Ti，TiW，Cr和Cu之一的光刻图案的UBM粘附层，形成 在UBM粘合层上方的心轴层，光刻图案化心轴层以形成孔，通过溅射，蒸发，物理气相沉积，焊波或注射成型在孔中沉积焊料层，通过CMP平坦化焊料层， 去除心轴层，回流焊料以焊接焊料以形成球互连，并将第二衬底与I / O焊盘接合到球互连。

公开(公告)号：US07365001B2

公开(公告)日：2008-04-29

申请号：US10735845

申请日：2003-12-16

申请人： Chih-Chao Yang ,  Louis L. Hsu ,  Keith Kwong Hon Wong ,  Timothy Joseph Dalton ,  Carl Radens ,  Larry Clevenger

发明人： Chih-Chao Yang ,  Louis L. Hsu ,  Keith Kwong Hon Wong ,  Timothy Joseph Dalton ,  Carl Radens ,  Larry Clevenger

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76862 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making a diffusion barrier for a interconnect structure. The method comprises: providing a conductive line in a bottom dielectric trench; depositing a sacrificial liner on the cap layer; depositing an interlayer dielectric; forming a trench and a via in the top interlayer dielectric; and removing a portion of the cap layer and the sacrificial layer proximate to the bottom surface of the via. The removed portions of the cap layer and sacrificial layer deposit predominantly along the lower sidewalls of the via. The conductive line is in contact with a cap layer, and the sacrificial layer is in contact with the cap layer. The invention is also directed to the interconnect structures resulting from the inventive process.

摘要翻译： 制造互连结构的扩散阻挡层的方法。 该方法包括：在底部电介质沟槽中提供导线; 在所述盖层上沉积牺牲衬垫; 沉积层间电介质; 在顶层间电介质中形成沟槽和通孔; 以及去除靠近通孔底表面的覆盖层和牺牲层的一部分。 盖层和牺牲层的去除部分主要沿着通孔的下侧壁沉积。 导线与盖层接触，牺牲层与盖层接触。 本发明还涉及由本发明方法产生的互连结构。

公开(公告)号：US20070222015A1

公开(公告)日：2007-09-27

申请号：US11750423

申请日：2007-05-18

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

IPC分类号： H01L31/0352

CPC分类号： H01L31/105 ,  H01L31/03529 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： Trench type PIN photodetectors are formed by etching two sets of trenches simultaneously in a semiconductor substrate, the wide trenches having a width more than twice as great as the narrow trenches by a process margin; conformally filling both types of trenches with a sacrificial material doped with a first dopant and having a first thickness slightly greater than one half the width of the narrow trenches, so that the wide trenches have a remaining central aperture; stripping the sacrificial material from the wide trenches in an etch that removes a first thickness, thereby emptying the wide trenches; a) filling the wide trenches with a second sacrificial material of opposite polarity; or b) doping the wide trenches from the ambient such as by gas phase doping, plasma doping, ion implantation, liquid phase doping, infusion doping and plasma immersion ion implantation; diffusing the dopants into the substrate, forming p and n regions of the PIN diode; removing the first and the second sacrificial materials, and filling both the wide and the narrow sets of trenches with the same conductive material in contact with the diffused p and n regions.

摘要翻译： 通过在半导体衬底中同时蚀刻两组沟槽形成沟槽型PIN光电检测器，宽沟槽的宽度是窄沟槽的两倍以上的加工余量; 用掺杂有第一掺杂剂的牺牲材料保形地填充两种类型的沟槽，并且具有略大于窄沟槽宽度的一半的第一厚度，使得宽沟槽具有剩余的中心孔径; 在去除第一厚度的蚀刻中从宽的沟槽剥离牺牲材料，从而排空宽的沟槽; a）用相反极性的第二牺牲材料填充宽的沟槽; 或b）通过气相掺杂，等离子体掺杂，离子注入，液相掺杂，浸渍掺杂和等离子体浸入离子注入等方式，从环境中掺杂宽沟槽; 将掺杂剂扩散到衬底中，形成PIN二极管的p区和n区; 去除第一和第二牺牲材料，并用与扩散的p和n区域接触的相同导电材料填充宽和窄的沟槽组。

公开(公告)号：US20060292789A1

公开(公告)日：2006-12-28

申请号：US11468543

申请日：2006-08-30

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

IPC分类号： H01L21/8242 ,  H01L29/94

CPC分类号： H01L21/3081 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087

摘要： A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench.

摘要翻译： 提供一种用于形成围绕半导体衬底中的沟槽的一部分的环的结构和方法，所述套环具有与邻近所述沟槽的下部设置的掩埋板的顶部边缘自对准的下边缘。

公开(公告)号：US20060252226A1

公开(公告)日：2006-11-09

申请号：US11485599

申请日：2006-07-12

申请人： Zarchary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

发明人： Zarchary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/76

CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/1087 ,  H01L27/1203

摘要： The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.

公开(公告)号：US20060124936A1

公开(公告)日：2006-06-15

申请号：US10905002

申请日：2004-12-09

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

IPC分类号： H01L29/786 ,  H01L21/8242

CPC分类号： H01L29/78642 ,  H01L27/10864 ,  H01L27/1087

摘要： A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the lithographic pattern for the active area, in particular a DRAM cell with a vertical transistor.

摘要翻译： 在半导体衬底中形成具有沟槽电容器和垂直晶体管的存储单元的方法包括提供具有平行于第一晶片轴的[010]轴的下基板的键合半导体晶片的步骤，以及具有 相对于晶片轴线定向成四十五度的[010]轴，两者通过一层粘合绝缘体连接; 蚀刻通过上层和下衬底的沟槽; 扩大沟槽的下部并将沟槽的上部的横截面从八边形转换为矩形，从而降低对沟槽光刻和有源区光刻之间对准误差的敏感性。 替代方案采用具有由（111）晶体结构和相同上部形成的下基板的键合半导体晶片。 应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻图案之间的未对准变得不敏感的垂直晶体管。

公开(公告)号：US20060108651A1

公开(公告)日：2006-05-25

申请号：US10904660

申请日：2004-11-22

申请人： Huilong Zhu ,  Lawrence Clevenger ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Kaushik Kumar ,  Carl Radens ,  Dureseti Chidambarrao

发明人： Huilong Zhu ,  Lawrence Clevenger ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Kaushik Kumar ,  Carl Radens ,  Dureseti Chidambarrao

IPC分类号： H01L29/94

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L29/0843 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： A novel transistor structure and method for fabrication the same. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. The method for fabricating the transistor structure starts out with a planar semiconductor layer and a gate stack on top of the semiconductor layer. Then, top regions of the semiconductor layer on opposing sides of the gate stack are removed. Then, regions beneath the removed regions are doped to form lowered S/D regions of the transistor structure

摘要翻译： 一种新颖的晶体管结构及其制造方法。 新颖的晶体管结构包括顶表面低于晶体管结构的沟道区的顶表面的第一和第二源极/漏极（S / D）区域。 用于制造晶体管结构的方法从在半导体层顶部的平面半导体层和栅叠层开始。 然后，去除栅极堆叠的相对侧上的半导体层的顶部区域。 然后，去除区域下方的区域被掺杂以形成晶体管结构的降低的S / D区域

公开(公告)号：US20060081986A1

公开(公告)日：2006-04-20

申请号：US10964882

申请日：2004-10-14

申请人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L23/52

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

摘要翻译： 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。