公开(公告)号：US5844370A

公开(公告)日：1998-12-01

申请号：US706295

申请日：1996-09-04

Applicant: David A. Cathey ,  Glen E. Hush ,  Manny K. F. Ma ,  Craig M. Dunham ,  David A. Zimlich

Inventor： David A. Cathey ,  Glen E. Hush ,  Manny K. F. Ma ,  Craig M. Dunham ,  David A. Zimlich

IPC: H01J29/04 ,  G09G3/20 ,  G09G3/22 ,  H01J3/02 ,  H01J31/12 ,  H01J19/24

CPC classification number: H01J31/127 ,  H01J3/022 ,  H01J2201/319 ,  H01J2329/92

Abstract: A field emission display includes electrostatic discharge protection circuits coupled to an emitter substrate and an extraction grid. In the preferred embodiment, the electrostatic discharge circuit includes diodes reverse biased between grid sections and a first reference potential or between row lines and a second reference potential. The diodes provide a current path to discharge static voltage and thereby prevent a high voltage differential from being maintained between the emitter sets and the extraction grids. The diodes thereby prevent the emitter sets from emitting electrons at a high rate that may damage or destroy the emitter sets. In one embodiment, the diodes are coupled directly between the grid sections and the row lines. In one embodiment, the diodes are formed in an insulative layer carrying the grid sections. In another embodiment, the diodes are integrated into the emitter substrate.

公开(公告)号：US5827101A

公开(公告)日：1998-10-27

申请号：US40129

申请日：1998-03-17

Applicant: David A. Cathey ,  Charles M. Watkins ,  James J. Hofmann

Inventor： David A. Cathey ,  Charles M. Watkins ,  James J. Hofmann

IPC: H01J9/22 ,  H01J29/08 ,  H01J29/18 ,  H01J29/89 ,  H01J31/12 ,  H01J29/32

CPC classification number: H01J29/896 ,  H01J29/085 ,  H01J31/127 ,  H01J2329/08 ,  H01J2329/892

Abstract: An anode of a flat panel display besides having a glass substrate, a patterned black grille on the substrate, a conductive layer covering the grille and the substrate, and a phosphor layer covering, also has one or more additional transparent layers that reduce the reflectance of the flat panel display from 14% down to 1%-4%. These additional layers are placed between the black matrix grille and the substrate, and between the conductive layer and phosphor layer. The two additional layers are selected and designed to reduce the reflectance that occurs at these respective interfaces.

Abstract translation: 平板显示器的阳极除了具有玻璃基板，基板上的图案化黑色格栅，覆盖格栅和基板的导电层和覆盖的荧光体层之外，还具有一个或多个附加的透明层，其降低了反射率 平板显示器从14％下降到1％-4％。 这些附加层被放置在黑矩阵格栅和基板之间以及导电层和荧光体层之间。 选择和设计两个附加层以减少在这些各个界面处发生的反射率。

公开(公告)号：US5766053A

公开(公告)日：1998-06-16

申请号：US690012

申请日：1996-07-31

Applicant: David A. Cathey ,  Charles Watkins

Inventor： David A. Cathey ,  Charles Watkins

IPC: H01J29/90 ,  H01J29/94 ,  H01J31/12 ,  H01J9/39

CPC classification number: H01J29/94 ,  H01J29/90 ,  H01J31/127 ,  H01J2329/8625 ,  H01J2329/92

Abstract: A flat-panel field emission display comprises a luminescent faceplate, a rigid backplate, and an interposed or sandwiched emitter or cathode plate. A positioning spacer or connector ridge is formed on the rear surface of the faceplate to space the cathode plate a fixed distance behind the faceplate. A peripheral seal is formed between the faceplate and the backplate. The faceplate, backplate, and peripheral seal define an evacuated internal space which contains the cathode plate. The backplate is spaced behind the cathode plate to create a rearward vacuum space in which a getter is located.

Abstract translation: 平板场发射显示器包括发光面板，刚性背板以及插入或夹持的发射器或阴极板。 在面板的后表面上形成定位间隔件或连接器脊，以使阴极板在面板后面固定距离。 在面板和背板之间形成周边密封。 面板，背板和外围密封件限定了包含阴极板的抽真空的内部空间。 背板在阴极板之后隔开，以形成一吸气剂位于其中的向后真空空间。

公开(公告)号：US5734226A

公开(公告)日：1998-03-31

申请号：US290633

申请日：1994-08-15

Applicant: David A. Cathey

Inventor： David A. Cathey

IPC: H01J29/94 ,  G09G3/00

CPC classification number: H01J29/94 ,  H01J2329/00

Abstract: A wire serves as a gettering material which is wire-bonded to electrical connections which lead outside of a vacuum sealed package. The wire can be activated to create and maintain a high integrity vacuum environment. The "getter" can be either heat activated or evaporated by the passing of an AC or DC current through the wire.

Abstract translation: 线用作吸气材料，其被引线接合到引导到真空密封包装之外的电连接。 电线可以被激活以产生和保持高完整性的真空环境。 “吸气剂”可以通过交流或直流电流通过电线而被激活或蒸发。

公开(公告)号：US5537738A

公开(公告)日：1996-07-23

申请号：US386646

申请日：1995-02-10

Applicant: David A. Cathey ,  Charles Watkins ,  Derek Gochnour

Inventor： David A. Cathey ,  Charles Watkins ,  Derek Gochnour

IPC: H01J9/34 ,  H01J9/24 ,  H01J9/26 ,  H01J9/32 ,  H01J9/36 ,  H01L21/60 ,  H01L21/98 ,  H01L23/538 ,  H05K3/32 ,  H05K3/36

CPC classification number: H01L25/50 ,  H01J9/241 ,  H01J9/261 ,  H01J9/32 ,  H01J9/36 ,  H01L23/5385 ,  H01J2329/8625 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H05K3/328 ,  H05K3/368 ,  Y10T29/49126

Abstract: The disclosure describes a method of attaching and electrically connecting first and second planar substrates, wherein the first and second substrates have inwardly-facing surfaces with matching patterns of bond pads. The method includes adjusting a wire bonder's tear length to a setting which leaves a projecting tail of severed bond wire at a terminating wedge bond connection. Further steps include making a wedge bond to an individual bond pad of the first planar substrate with bond wire from the wire bonder, and then severing the bond wire adjacent said wedge bond. The adjusted tear length of the wire bonder results in a tail of severed bond wire which projects from said wedge bond and said individual bond pad. Subsequent steps include positioning the first and second planar substrates with their inwardly facing surfaces facing each other, aligning the matching bond pad patterns of the first and second planar substrates, and pressing the first and second planar substrates against each other. The bond wire tail deforms between the bond pads of the first and second planar substrates to conductively bond therebetween.

Abstract translation: 本公开描述了一种附接和电连接第一和第二平面基板的方法，其中第一和第二基板具有具有匹配的接合焊盘图案的向内表面。 该方法包括将引线接合器的撕裂长度调整到在终止楔形接合连接处留下断开的接合线的突出尾部的设置。 进一步的步骤包括使用来自引线接合器的接合线与第一平面基板的单独接合焊盘楔合，然后切断邻近所述楔形键的接合线。 引线接合器的经调整的撕裂长度导致从所述楔形键和所述单独接合焊盘突出的断开的接合线的尾部。 随后的步骤包括将第一和第二平面基板定位成其面向彼此的向内表面，使第一和第二平面基板的匹配接合焊盘图案对齐，并将第一和第二平面基板相互压制。 接合线尾部在第一和第二平面基板的接合焊盘之间变形，以在它们之间导电地结合。

公开(公告)号：US5532177A

公开(公告)日：1996-07-02

申请号：US89166

申请日：1993-07-07

Applicant: David A. Cathey

Inventor： David A. Cathey

IPC: H01J1/304 ,  H01J9/02 ,  H01L21/265

CPC classification number: H01J1/3044 ,  H01J1/3042 ,  H01J9/025 ,  H01J2201/30403 ,  Y10S148/116 ,  Y10S148/172 ,  Y10S438/978

Abstract: Electron emitters and a method of fabricating emitters which have a concentration gradient of impurities, such that the highest concentration of impurities is at the apex of the emitters, and decreases toward the base of the emitters. The method comprises the steps of doping, patterning, etching, and oxidizing the substrate, thereby forming the emitters having impurity gradients.

Abstract translation: 电子发射体和制造具有杂质浓度梯度的发射体的方法，使得最高浓度的杂质位于发射体的顶点，朝向发射体的基底减小。 该方法包括掺杂，图案化，蚀刻和氧化衬底的步骤，从而形成具有杂质梯度的发射体。

公开(公告)号：US5328810A

公开(公告)日：1994-07-12

申请号：US981976

申请日：1992-11-25

Applicant: Tyler A. Lowrey ,  Randal W. Chance ,  David A. Cathey

Inventor： Tyler A. Lowrey ,  Randal W. Chance ,  David A. Cathey

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  G03C5/00

CPC classification number: H01L21/3088 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  Y10S148/106

Abstract: The process starts with a primary mask, which may be characterized as a pattern of parallel, photoresist strips having substantially vertical edges, each having a minimum feature width F, and being separated from neighboring strips by a minimum space width which is also approximately equal to F. From this primary mask, a set of expendable mandrel strips is created either directly or indirectly. The set of mandrel strips may be characterized as a pattern of parallel strips, each having a feature width of F/2, and with neighboring strips being spaced from one another by a space width equal to 3/2F. A conformal stringer layer is then deposited. The stringer layer material is selected such that it may be etched with a high degree of selectivity with regard to both the mandrel strips and an underlying layer which will ultimately be patterned using a resultant, reduced-pitch mask. The stringer layer is then anisotropically etched to the point where the top of each mandrel strip is exposed. The mandrel strips are then removed with an appropriate etch. A pattern of stringer strips remains which can then be used as a half-pitch mask to pattern the underlying layer. This process may also be repeated, starting with the half-pitch mask and creating a quarter-pitch mask, etc. As can be seen, this technique permits a reduction in the minimum pitch of the primary mask by a factor of 2.sup.-N (where N is an integer 1, 2, 3, . . . ).

Abstract translation: 该过程从初始掩模开始，其可以被表征为具有基本垂直边缘的平行的光致抗蚀剂条带的图案，每个具有最小特征宽度F，并且与相邻条带分开最小空间宽度，其最大空间宽度也近似等于 F.从这个主要面罩，直接或间接地创建一组消耗性的芯棒条。 芯棒条的组可以被表征为平行条带的图案，每个条带具有F / 2的特征宽度，并且相邻条带彼此间隔开等于3 / 2F的空间宽度。 然后沉积保形纵梁层。 选择桁条层材料，使得可以以相对于芯棒条和下一层的高度选择性蚀刻，其将最终使用所得到的减少节距的掩模进行图案化。 然后将纵梁层各向异性地蚀刻到每个芯棒条的顶部暴露的点。 然后用适当的蚀刻去除心轴条。 留下一条桁条条纹，然后可以将其作为半间距掩模用于对下层进行图案化。 该过程也可以重复，从半间距掩模开始并产生四分之一间距掩模等。可以看出，该技术允许将初级掩模的最小间距减小2-N倍（ 其中N是整数1,2,3，...）。

公开(公告)号：US5298463A

公开(公告)日：1994-03-29

申请号：US870603

申请日：1992-04-16

Applicant: Gurtej S. Sandhu ,  David A. Cathey

Inventor： Gurtej S. Sandhu ,  David A. Cathey

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768 ,  H01L21/465

CPC classification number: H01L21/28512 ,  H01L21/31111 ,  H01L21/76802 ,  Y10S438/97

Abstract: A method of processing a semiconductor wafer includes: a) fabricating a wafer to define a plurality of conductive regions, the conductive regions having outer surfaces positioned at varying elevations on the wafer thereby defining at least one high elevation conductive region and at least one low elevation conductive region; b) providing a planarized insulating dielectric layer atop the wafer; c) patterning the insulating dielectric layer for defining a plurality of contact openings through the insulating dielectric to selected conductive regions at the varying elevations; d) first etching the plurality of contact openings into the patterned insulating layer downwardly to stop at the high elevation conductive region outer surface to which electrical contact is to be made; e) after first etching, selectively depositing a layer of an etch stop material to a selected thickness atop the outer surface of the high elevation conductive region; and f) second etching the plurality of contact openings into the patterned insulating material to the low elevation conductive region outer surface to which electrical contact is to be made using the selectively deposited etch stop material layer over the high elevation conductive region as an etch stop protecting layer during such second etching. Photoresist may or may not remain in place during the second etching depending on insulating dielectric layer thicknesses.

Abstract translation: 一种处理半导体晶片的方法包括：a）制造晶片以限定多个导电区域，所述导电区域具有位于晶片上不同高度的外表面，从而限定至少一个高仰角导电区域和至少一个低仰角 导电区域 b）在晶片顶上提供平坦化的绝缘介电层; c）图案化所述绝缘电介质层，以在所述不同高度处限定通过所述绝缘电介质到选定导电区域的多个接触开口; d）首先将多个接触开口蚀刻到图案化的绝缘层中，以在要形成电接触的高高度导电区域外表面停止; e）在第一蚀刻之后，在所述高高度导电区域的外表面顶部选择性地沉积蚀刻停止材料层至所选择的厚度; 以及f）使用在高仰角导电区域上的选择性沉积的蚀刻停止材料层将多个接触开口第二蚀刻到图案化的绝缘材料中到达低电导率区域外表面，在其上进行电接触作为蚀刻停止保护 在这样的第二蚀刻期间。 根据绝缘电介质层厚度，光刻胶在第二次蚀刻期间可以或不会保持在适当的位置。

公开(公告)号：US5260517A

公开(公告)日：1993-11-09

申请号：US942951

申请日：1992-09-09

Applicant: David A. Cathey

Inventor： David A. Cathey

IPC: H01L23/528 ,  H01L23/532 ,  H05K1/00

CPC classification number: H01L23/53223 ,  H01L23/5283 ,  H01L2924/0002

Abstract: An interconnect lead (12) has trenches (28) that function as stress joints to inhibit the formation of stress related defects, such as cracks and hillocks. The interconnect lead is formed by a continuous layer (18) of a refractory metal alloy and a segmented layer (22) of an aluminum alloy. The stress joints are formed by using a high resolution microlithographic process (48) to etch the narrow trenches in a transverse direction to the length of the conductor through the aluminum layer.

Abstract translation: 互连引线（12）具有作为应力接头的沟槽（28），以阻止形成应力相关缺陷，例如裂纹和小丘。 互连引线由难熔金属合金的连续层（18）和铝合金的分段层（22）形成。 应力接合是通过使用高分辨率微光刻工艺（48）来形成的，以便通过铝层在横向方向上蚀刻窄沟槽。

公开(公告)号：US5259799A

公开(公告)日：1993-11-09

申请号：US977477

申请日：1992-11-17

Applicant: Trung T. Doan ,  Tyler A. Lowrey ,  David A. Cathey ,  J. Brett Rolfson

Inventor： Trung T. Doan ,  Tyler A. Lowrey ,  David A. Cathey ,  J. Brett Rolfson

IPC: H01J9/02 ,  H01J9/04

CPC classification number: H01J9/025 ,  H01J2209/0226 ,  H01J2329/00

Abstract: A selective etching and chemical mechanical planarization process for the formation of self-aligned gate and focus ring structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a first conformal layer, iii) deposited with a conductive material layer, iv) deposited with a second conformal insulating layer, v) deposited with a focus electrode ring material layer, vi) optionally deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose a portion of the second conformal layer, viii) etched to form a self-aligned gate and focus ring, and thereby expose the emitter tip, afterwhich xi) the emitter tip may be coated with a low work function material.

Abstract translation: 用于形成围绕用于场发射显示器中的电子发射尖端的自对准栅极和聚焦环结构的选择性蚀刻和化学机械平面化工艺，其中发射尖端i）可选地通过氧化锐化，ii）沉积有第一 保留层，iii）沉积有导电材料层，iv）沉积有第二共形绝缘层，v）沉积有焦点电极环材料层，vi）任选地沉积有缓冲材料，vii）用化学机械平面化 （CMP）步骤，以暴露第二共形层的一部分，viii）蚀刻以形成自对准栅极和聚焦环，从而暴露发射极尖端，之后xi）发射极尖端可以被涂覆有低功函数 材料。