公开(公告)号：US20170110465A1

公开(公告)日：2017-04-20

申请号：US14884747

申请日：2015-10-15

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ping ZHENG ,  Eng Huat TOH ,  Kiok Boone Elgin QUEK ,  Yuan SUN

IPC: H01L27/112 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L27/11206 ,  B82Y10/00 ,  B82Y40/00 ,  H01L23/5252 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7851 ,  Y10S977/765 ,  Y10S977/888 ,  Y10S977/943

Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with at least a first region for accommodating an anti-fuse based memory cell. A fin structure is formed in the first region. The fin structure includes top and bottom fin portions and includes channel and non-channel regions defined along the length of the fin structure. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving the top fin portion exposed. At least a portion of the exposed top fin portion in the channel region is processed to form a sharpened tip profile at top of the fin. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the channel region of the fin structure.

公开(公告)号：US20170084736A1

公开(公告)日：2017-03-23

申请号：US14856574

申请日：2015-09-17

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat TOH ,  Xinfu LIU ,  Xueming Dexter TAN

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/7816 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66484 ,  H01L29/66681 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/7835

Abstract: High voltage devices and methods for forming a high voltage device are disclosed. The high voltage device includes a substrate prepared with a device isolation region. The device isolation region defines a device region. The device region includes at least first and second source/drain regions and a gate region defined thereon. A device well is disposed in the device region. The device well encompasses the at least first and second source/drain regions. A primary gate and at least one secondary gate adjacent to the primary gate are disposed in the gate region. The at least first and second source/drain regions are displaced from first and second sides of the primary gate.

公开(公告)号：US20160247857A1

公开(公告)日：2016-08-25

申请号：US15144844

申请日：2016-05-03

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Shyue Seng TAN ,  Eng Huat TOH ,  Elgin QUEK

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: A RRAM device having a diode device structure coupled to a variable resistance layer is disclosed. The diode device structure can either be embedded into or fabricated over the substrate. A memory device having an array of said RRAM devices can be fabricated with multiple common bit lines and common word lines.

Abstract translation: 公开了一种具有耦合到可变电阻层的二极管器件结构的RRAM器件。 二极管器件结构可以嵌入衬底或者在衬底上制造。 具有所述RRAM器件的阵列的存储器件可以用多个公共位线和公共字线制造。

公开(公告)号：US20160225423A1

公开(公告)日：2016-08-04

申请号：US15012798

申请日：2016-02-01

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Vinayak Bharat NAIK ,  Eng Huat TOH ,  Kiok Boone Elgin QUEK

IPC: G11C11/16 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02

CPC classification number: G11C11/161 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/18 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a substrate defined with a memory cell region. A cell selector unit is defined on the substrate. The cell selector unit includes at least one select transistor. A storage element which includes a magnetic tunnel junction (MTJ) element is coupled to the selector unit. The MTJ element includes a free layer, a fixed layer and a tunnel barrier sandwiched between the fixed and free layers. A spin-orbit-torque (SOT) layer is coupled to the selector unit and is in direct contact with the free layer. A strain induced layer is coupled to a digital line (DL) and is in direct contact with the SOT layer. When the DL is activated, an electric field applied to the strain induced layer induces a strain on the SOT layer.

Abstract translation: 公开了用于形成存储单元的存储单元和方法。 存储单元包括由存储单元区限定的衬底。 在基板上限定单元选择器单元。 单元选择器单元包括至少一个选择晶体管。 包括磁性隧道结（MTJ）元件的存储元件被耦合到选择器单元。 MTJ元件包括夹在固定层和自由层之间的自由层，固定层和隧道屏障。 自旋轨道转矩（SOT）层耦合到选择器单元并与自由层直接接触。 应变感应层耦合到数字线（DL）并与SOT层直接接触。 当DL被激活时，施加到应变感应层的电场在SOT层上引起应变。

公开(公告)号：US20160181440A1

公开(公告)日：2016-06-23

申请号：US15041619

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Shyue Seng TAN ,  Eng Huat TOH ,  Elgin Kiok Boone QUEK

IPC: H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L29/40117 ,  H01L29/402 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/516 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66681 ,  H01L29/66833 ,  H01L29/7816

Abstract: Methods for forming field effect transistors (FETs) with improved ON/OFF current ratios in addition to short charging times and the resulting devices are disclosed. Embodiments include forming a gate oxide layer above a channel region in a substrate, forming a partial self-adjusting threshold voltage layer above a drain-side end of the gate oxide layer, and forming a gate above the partial self-adjusting threshold voltage layer and the gate oxide layer.

Abstract translation: 公开了除了充电时间短以外，具有改善的ON / OFF电流比的场效应晶体管（FET）的方法以及所得到的器件。 实施例包括在衬底中的沟道区域上方形成栅极氧化层，在栅极氧化物层的漏极侧端部上形成部分自调节阈值电压层，以及在部分自调节阈值电压层上方形成栅极， 栅氧化层。

公开(公告)号：US20160079310A1

公开(公告)日：2016-03-17

申请号：US14483160

申请日：2014-09-11

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xuan Anh TRAN ,  Eng Huat TOH ,  Shyue Seng TAN ,  Yuan SUN ,  Elgin Kiok Boone QUEK

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/226 ,  H01L27/2445 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

Abstract: Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element.The selector includes a well of a first polarity type disposed in the substrate, a region of a second polarity type disposed over the well and in the substrate, and first and second regions of the first polarity type disposed adjacent to the region of the second polarity type. The storage element includes a programmable resistive layer disposed on the region of the second polarity type and an electrode disposed over the programmable resistive layer.

Abstract translation: 介绍了存储器件及其制造方法。 存储器件，衬底和具有至少一个选择器和存储元件的存储器单元。 选择器包括设置在基板中的第一极性类型的阱，设置在阱和衬底中的第二极性类型的区域，以及邻近第二极性区域设置的第一极性类型的第一和第二区域 类型。 存储元件包括设置在第二极性类型的区域上的可编程电阻层和设置在可编程电阻层上的电极。

公开(公告)号：US20150236034A1

公开(公告)日：2015-08-20

申请号：US14704004

申请日：2015-05-05

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat TOH ,  Khee Yong LIM ,  Shyue Seng TAN ,  Elgin QUEK

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/792 ,  H01L29/49

CPC classification number: H01L27/11568 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A memory device requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: a substrate; a gate stack on the substrate; a source and drain in the substrate at opposite sides, respectively, of the gate stack; a source extension region in the substrate adjacent the source region, wherein no drain extension region is formed on the other side of the gate stack; a tunnel oxide liner on the substrate at each side of the gate stack and on side surfaces of the gate stack; and a charge-trapping (CT) spacer on each tunnel oxide liner.

Abstract translation: 公开了一种不需要或最小的附加掩模的存储器件，其具有低成本，小占地面积和多次编程能力。 实施例包括：基板; 衬底上的栅极堆叠; 分别在栅叠层的相对侧的衬底中的源极和漏极; 邻近所述源极区域的所述衬底中的源极延伸区域，其中在所述栅极叠层的另一侧上不形成漏极延伸区域; 栅极堆叠的每一侧的基板上以及栅极堆叠的侧表面上的隧道氧化物衬垫; 和每个隧道氧化物衬垫上的电荷捕获（CT）间隔物。

公开(公告)号：US20150221651A1

公开(公告)日：2015-08-06

申请号：US14173825

申请日：2014-02-06

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat TOH ,  Danny Pak-Chum SHUM ,  Shyue Seng TAN

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/161 ,  H01L21/762 ,  H01L21/265 ,  H01L21/02 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L27/10802 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/3065 ,  H01L21/76243 ,  H01L21/76267 ,  H01L27/11 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/161 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7841

Abstract: One-transistor (1T) volatile memory devices and manufacturing methods thereof are provided. The device includes a substrate having top and bottom surfaces and an isolation buffer layer disposed below the top substrate surface. The isolation buffer layer is an amorphized portion of the substrate. An area of the substrate between the isolation buffer layer and the top substrate surface serves as a body region of a transistor. The device also includes a transistor disposed over the substrate. The transistor includes a gate disposed on the top substrate surface, and first and second diffusion regions disposed in the body region adjacent to first and second sides of the gate.

公开(公告)号：US20150137060A1

公开(公告)日：2015-05-21

申请号：US14084633

申请日：2013-11-20

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Yuan SUN ,  Eng Huat TOH

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/66 ,  H01L29/872

CPC classification number: H01L27/2409 ,  H01L27/2463 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

Abstract: Devices and methods for forming a device are disclosed. The device includes a substrate and a selector diode disposed over the substrate. The diode includes first and second terminals. The first terminal is disposed between the second terminal and the substrate. The diode includes a Schottky Barrier (SB) disposed at about an interface of the first and second terminals. The SB includes a tunable SB height defined by a SB region having segregated dopants. The device includes a memory element disposed over and coupled to the selector diode.

Abstract translation: 公开了用于形成装置的装置和方法。 该器件包括设置在衬底上的衬底和选择二极管。 二极管包括第一和第二端子。 第一端子设置在第二端子和衬底之间。 二极管包括设置在第一和第二端子的界面附近的肖特基势垒（SB）。 SB包括由具有分离的掺杂剂的SB区域限定的可调谐SB高度。 该器件包括设置在选择二极管上并耦合到选择二极管的存储元件。

公开(公告)号：US20150123068A1

公开(公告)日：2015-05-07

申请号：US14522609

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat TOH ,  Elgin QUEK ,  Shyue Seng TAN

IPC: H01L45/00

CPC classification number: H01L45/1233 ,  H01L45/04 ,  H01L45/06 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1675 ,  H01L45/1691

Abstract: Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is less than a lithographic resolution. The fin stack layers are patterned using the spacers as a mask to form fin stacks. The fin stacks contact the bottom electrodes. An interlevel dielectric (ILD) layer is formed on the substrate. The ILD layer fills spaces around the fin stacks. An upper electrode level is formed on the ILD layer. The upper electrode level has top electrodes in contact with the fin stacks. The electrodes and fin stacks form fin-type memory cells.

Abstract translation: 公开了用于形成装置的存储装置和方法。 提供了制备具有与底部电极的较低电极电平的衬底。 鳍状堆叠层形成在下部电极层上。 垫片形成在翅片堆叠层的顶部。 间隔物的宽度小于光刻分辨率。 使用间隔件作为掩模来对翅片堆叠层进行图案化以形成翅片堆叠。 鳍片堆叠接触底部电极。 在衬底上形成层间电介质（ILD）层。 ILD层填充散热片堆叠周围的空间。 在ILD层上形成上电极层。 上电极电平具有与散热片堆叠接触的顶部电极。 电极和散热片堆叠形成鳍式存储单元。