公开(公告)号：US09947767B1

公开(公告)日：2018-04-17

申请号：US15416566

申请日：2017-01-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robinhsinku Chao ,  ChoongHyun Lee ,  Heng Wu ,  Chun W. Yeung ,  Jingyun Zhang

IPC: H01L21/335 ,  H01L29/66 ,  H01L21/324 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/02247 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78696

Abstract: A semiconductor devices and methods of forming the same include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.

公开(公告)号：US20180089479A1

公开(公告)日：2018-03-29

申请号：US15603982

申请日：2017-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hemanth Jagannathan ,  ChoongHyun Lee ,  Richard G. Southwick, III

IPC: G06K7/10 ,  G06K7/14

CPC classification number: G06K7/10574 ,  G06K7/1413 ,  H01L21/28238 ,  H01L21/28255 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top surface within the gate portion, and an nFET region including a Si channel. The method includes subjecting both the pFET and nFET regions to a single high-temperature anneal process thereby avoiding the need for an additional spike anneal process at RMG module.

公开(公告)号：US20180005904A1

公开(公告)日：2018-01-04

申请号：US15198128

申请日：2016-06-30

Applicant: International Business Machines Corporation

Inventor： ChoongHyun Lee ,  Injo Ok ,  Soon-Cheon Seo

IPC: H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L27/092 ,  H01L29/205 ,  H01L29/16

CPC classification number: H01L21/823885 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/205

Abstract: A semiconductor structure includes a first nanowire of a first material formed on a substrate, at least a second nanowire of a second material different than the first material formed on the substrate and a common gate stack surrounding the first nanowire and the second nanowire. The first nanowire and the second nanowire are vertical with respect to a horizontal plane of the substrate. The first material may be indium gallium arsenide (InGaAs) and the first nanowire may form part of an NFET channel of a CMOS device, while the second material may be germanium (Ge) and the second nanowire may form part of a PFET channel of the CMOS device.

公开(公告)号：US20230170415A1

公开(公告)日：2023-06-01

申请号：US17456894

申请日：2021-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chen Zhang ,  ChoongHyun Lee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/1033 ,  H01L29/66666

Abstract: A semiconductor structure including a bottom source drain region arranged on a substrate, a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region, a metal gate disposed around the semiconductor channel region, a top source drain region above the semiconductor channel region, an amorphous silicon layer directly on top of the metal gate, and an oxidation layer directly on top of the amorphous silicon layer, where the amorphous silicon layer and the oxidation layer together completely separate the metal gate from a surrounding interlevel dielectric layer.

公开(公告)号：US11322408B2

公开(公告)日：2022-05-03

申请号：US17130214

申请日：2020-12-22

Applicant: International Business Machines Corporation

Inventor： Nicolas Loubet ,  Richard A. Conti ,  ChoongHyun Lee

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L27/088 ,  H01L29/165 ,  H01L21/308 ,  H01L21/02

Abstract: A method of forming a semiconductor structure includes forming a semiconductor layer stack including a substrate and a nanosheet channel stack including alternating layers of a sacrificial material and a semiconducting material providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the semiconductor layer stack, forming a liner on sidewalls of the vertical fins, and forming a sacrificial epitaxial layer over the substrate surrounding the vertical fins. The method further includes replacing the sacrificial epitaxial layer with a first dielectric layer, removing the liner to form air gaps between the first dielectric layer and sidewalls of the vertical fins, and forming a second dielectric layer in the air gaps between the first dielectric layer and sidewalls of the vertical fins. The first and second dielectric layers provide shallow trench isolation regions surrounding sidewalls of the vertical fins below the nanosheet channel stack.

公开(公告)号：US11271106B2

公开(公告)日：2022-03-08

申请号：US16813105

申请日：2020-03-09

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Brent A. Anderson ,  ChoongHyun Lee ,  Hemanth Jagannathan

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

Abstract: A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor.

公开(公告)号：US11145555B2

公开(公告)日：2021-10-12

申请号：US16824801

申请日：2020-03-20

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  ChoongHyun Lee ,  Hemanth Jagannathan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265 ,  H01L27/092 ,  H01L21/324

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a substrate, and forming one or more vertical transport field-effect transistors from the plurality of fins, the plurality of fins providing channels for the one or more vertical transport field-effect transistors. The method also includes forming a gate stack for the one or more vertical transport field-effect transistors surrounding at least a portion of the plurality of fins, the gate stack including a gate dielectric formed over the plurality of fins, a work function metal layer formed over the gate dielectric, and a gate conductor formed over the work function metal layer. The gate stack comprises a box profile in an area between at least two adjacent ones of the plurality of fins.

公开(公告)号：US20210111077A1

公开(公告)日：2021-04-15

申请号：US17130214

申请日：2020-12-22

Applicant: International Business Machines Corporation

Inventor： Nicolas Loubet ,  Richard A. Conti ,  ChoongHyun Lee

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L27/088 ,  H01L29/165 ,  H01L21/308 ,  H01L21/02

Abstract: A method of forming a semiconductor structure includes forming a semiconductor layer stack including a substrate and a nanosheet channel stack including alternating layers of a sacrificial material and a semiconducting material providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the semiconductor layer stack, forming a liner on sidewalls of the vertical fins, and forming a sacrificial epitaxial layer over the substrate surrounding the vertical fins. The method further includes replacing the sacrificial epitaxial layer with a first dielectric layer, removing the liner to form air gaps between the first dielectric layer and sidewalls of the vertical fins, and forming a second dielectric layer in the air gaps between the first dielectric layer and sidewalls of the vertical fins. The first and second dielectric layers provide shallow trench isolation regions surrounding sidewalls of the vertical fins below the nanosheet channel stack.

公开(公告)号：US10957742B2

公开(公告)日：2021-03-23

申请号：US16539518

申请日：2019-08-13

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  ChoongHyun Lee ,  Seyoung Kim ,  Wilfried Haensch

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: Devices and methods are provided to construct resistive random-access (RRAM) array structures which comprise RRAM memory cells, wherein each RRAM memory cell is formed of multiple parallel-connected RRAM devices to reduce the effects of resistive switching variability of the RRAM memory cells.

公开(公告)号：US10910273B2

公开(公告)日：2021-02-02

申请号：US16284682

申请日：2019-02-25

Applicant: International Business Machines Corporation

Inventor： Nicolas Loubet ,  Richard A. Conti ,  ChoongHyun Lee

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L27/088 ,  H01L29/165 ,  H01L21/308 ,  H01L21/02

Abstract: A method of forming a semiconductor structure includes forming a semiconductor layer stack including a substrate and a nanosheet channel stack including alternating layers of a sacrificial material and a semiconducting material providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the semiconductor layer stack, forming a liner on sidewalls of the vertical fins, and forming a sacrificial epitaxial layer over the substrate surrounding the vertical fins. The method further includes replacing the sacrificial epitaxial layer with a first dielectric layer, removing the liner to form air gaps between the first dielectric layer and sidewalls of the vertical fins, and forming a second dielectric layer in the air gaps between the first dielectric layer and sidewalls of the vertical fins. The first and second dielectric layers provide shallow trench isolation regions surrounding sidewalls of the vertical fins below the nanosheet channel stack.