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    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE
    73.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE 有权
    具有元件分离区域的非挥发性半导体存储器件

    公开(公告)号：US20120168846A1

    公开(公告)日：2012-07-05

    申请号：US13421248

    申请日：2012-03-15

    申请人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

    发明人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11548 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/788

    摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

    摘要翻译： 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子 经由开口部与第一电极层连接。

    Method for programming a memory structure
    76.
    发明授权
    Method for programming a memory structure 有权
    用于编程存储器结构的方法

    公开(公告)号：US07855918B2

    公开(公告)日：2010-12-21

    申请号：US12144645

    申请日：2008-06-24

    申请人： Riichiro Shirota ,  Ching-Hsiang Hsu ,  Cheng-Jye Liu

    发明人： Riichiro Shirota ,  Ching-Hsiang Hsu ,  Cheng-Jye Liu

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3418

    摘要： A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.

    摘要翻译： 存储器结构包括位于相同位线并与第一存储器单元相邻的第一存储器单元和第二存储器单元。 每个存储单元包括衬底，源极，漏极，电荷存储器件和栅极。 一种用于对存储器结构进行编程的方法包括分别向第一存储单元和第二存储单元提供第一栅极偏置电压和第二栅极偏置电压，提高第一存储单元的沟道电压的绝对值以产生电子和空穴 通过栅极引起的漏极泄漏或带对带隧穿在第二存储单元的漏极处对，并将所产生的电子和空穴对的电子注入到第一存储单元的电荷存储装置中，以对第一存储单元 。

    Channel carrier discharging in a NAND flash memory on an insulating substrate or layer
    77.
    发明授权
    Channel carrier discharging in a NAND flash memory on an insulating substrate or layer 失效
    通道载体在绝缘基板或层上的NAND闪速存储器中放电

    公开(公告)号：US07791948B2

    公开(公告)日：2010-09-07

    申请号：US12165211

    申请日：2008-06-30

    申请人： Riichiro Shirota ,  Fumitaka Arai

    发明人： Riichiro Shirota ,  Fumitaka Arai

    IPC分类号： G11C16/02 ,  G11C16/06

    CPC分类号： G11C16/3431 ,  G11C16/0483 ,  G11C16/10

    摘要： A semiconductor memory device includes: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device insulating film buried therein; and NAND cell units formed on the active areas, each NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, both ends of each NAND cell unit being coupled to a source line and a bit line, wherein the device has such a carrier discharging mode as to discharge channel carriers in the NAND cell unit to at least one of the source line and the bit line.

    摘要翻译： 半导体存储器件包括：设置在绝缘基板或绝缘层上的半导体层; 在半导体层中限定的有源区域，其中埋设有器件绝缘膜; 以及形成在有源区上的NAND单元单元，每个NAND单元单元包括串联连接的多个电可重写和非易失性存储单元，每个NAND单元单元的两端耦合到源极线和位线，其中， 器件具有这样的载流子放电模式，以将NAND单元单元中的沟道载流子放电到源极线和位线中的至少一个。

    Semiconductor memory device improved in data writing
    79.
    发明授权
    Semiconductor memory device improved in data writing 失效
    半导体存储器件改进了数据写入

    公开(公告)号：US07616491B2

    公开(公告)日：2009-11-10

    申请号：US11738636

    申请日：2007-04-23

    申请人： Takeshi Kamigaichi ,  Riichiro Shirota

    发明人： Takeshi Kamigaichi ,  Riichiro Shirota

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  H01L27/115 ,  H01L27/11524

    摘要： A bit line is shared by first and second NAND units. First and second selection transistors are connected in series between the bit line and the first NAND unit. Third and fourth selection transistors are connected in series between the bit line and the second NAND unit. A control unit changes a first and second signals and a potential of the bit line from a first level to a second level higher than a first level, and changes the potential of the bit line from the second level to the first level after changing the first signal from the second level to the first level.

    摘要翻译： 位线由第一和第二NAND单元共享。 第一和第二选择晶体管串联在位线和第一NAND单元之间。 第三和第四选择晶体管串联在位线和第二NAND单元之间。 控制单元将第一和第二信号和位线的电位从第一电平改变到高于第一电平的第二电平，并且在改变第一电平之后将位线的电位从第二电平改变到第一电平 信号从第二级到第一级。