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公开(公告)号：US20180292990A1
公开(公告)日：2018-10-11
申请号：US16006192
申请日：2018-06-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Eric Lee , Qiang Tang , Ali Feiz Zarrin Ghalam , Hoon Choi , Daesik Song
CPC classification number: G06F3/061 , G06F3/0656 , G06F3/0679 , G06F12/0215 , G06F12/0802 , G06F2212/1016 , G06F2212/2022 , G06F2212/222 , G06F2212/7203 , G11C7/106 , G11C7/1066 , G11C7/222 , G11C16/26 , G11C16/32
Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and to latch data for output from the memory device in response to the second clock edge of the first clock signal.
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公开(公告)号：US10019170B2
公开(公告)日：2018-07-10
申请号：US15084979
申请日：2016-03-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Eric Lee , Qiang Tang , Ali Feiz Zarrin Ghalam , Hoon Choi , Daesik Song
CPC classification number: G06F3/061 , G06F3/0656 , G06F3/0679 , G06F12/0215 , G06F12/0802 , G06F2212/1016 , G06F2212/2022 , G06F2212/222 , G06F2212/7203 , G11C7/106 , G11C7/1066 , G11C7/222 , G11C16/26 , G11C16/32
Abstract: In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.
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公开(公告)号：US09767894B2
公开(公告)日：2017-09-19
申请号：US14299074
申请日：2014-06-09
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Qiang Tang , Xiaojiang Guo , Ramin Ghodsi
CPC classification number: G11C11/5628 , G06F3/0625 , G06F3/0659 , G06F3/0688 , G06F12/0246 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3404 , G11C16/3459 , G11C2211/5621 , G11C2211/5622
Abstract: Memories and methods for programming memories with multi-step programming pulses are provided. One method includes applying a plurality of programming pulses to cells of the memory device to be programmed, with each programming pulse of the plurality of programming pulses being configured to contribute towards programming a cell of the plurality of cells to each data state of a plurality of programmed data states. A first portion of each programming pulse is used to program certain cells towards a target data state associated with a first threshold voltage level, and a later portion of each programming pulse is used to program other cells towards a target data state associated with a second threshold voltage level that is lower than the first threshold voltage level.
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公开(公告)号：US09722489B1
公开(公告)日：2017-08-01
申请号：US15144682
申请日：2016-05-02
Applicant: Micron Technology, Inc.
Inventor： Xiaojiang Guo , Qiang Tang
IPC: G11C5/14 , H02M3/07 , G11C11/4074
CPC classification number: G11C5/147 , G11C5/145 , G11C11/4074 , G11C16/30
Abstract: Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first output, a second charge pump circuit configured to provide a second output, a plurality of coupling circuits configured to voltage couple and current couple the first output and the second output to a common node to provide a regulated voltage, and a feedback circuit configured to regulate the first output and the second output based on the regulated voltage.
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公开(公告)号：US20170169863A1
公开(公告)日：2017-06-15
申请号：US15444980
申请日：2017-02-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Qiang Tang
CPC classification number: G11C5/14 , G06F13/4072 , G06F13/4086 , H03H11/28 , H03K19/0005 , H03K19/017545 , H03K19/018557
Abstract: Apparatus include a data bus and a signal driver circuit having pluralities of first and second termination devices connected in parallel between a voltage node and an output node. Each of the termination devices is configured to be deactivated in response to control signals having a particular set of logic levels, and to be activated in response to control signals having a set of logic levels other than the particular set of logic levels. Activated second termination devices each exhibit respective resistances greater than a particular resistance of each activated first termination device. Methods include connecting a node of an apparatus to a first voltage node through a reference resistance, connecting the node to a second voltage node through a termination device, and comparing a resulting voltage level to a reference voltage different than half-way between voltage levels of the first and second voltage nodes.
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Patent Agency Ranking
公开(公告)号：US20170162269A1
公开(公告)日：2017-06-08
申请号：US15436289
申请日：2017-02-17
Applicant: Micron Technology, Inc.
Inventor： Feng Pan , Ramin Ghodsi , Qiang Tang
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/24 , G11C16/26
Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.
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公开(公告)号：US20160099048A1
公开(公告)日：2016-04-07
申请号：US14868604
申请日：2015-09-29
Applicant: Micron Technology, Inc.
Inventor： Qiang Tang , Feng Pan , Ramin Ghodsi , Mark A. Helm
IPC: G11C11/56
CPC classification number: G11C11/5642 , G11C7/14 , G11C29/021 , G11C29/028 , G11C2029/0409
Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.
Abstract translation: 描述了用于阈值电压（Vt）分布测定的装置和方法。 许多设备可以包括感测电路，其被配置为确定存储器单元阵列的源极线上的第一电流，第一电流对应于响应于第一感测而导通的一组存储器单元的第一数量的存储器单元 施加到访问线路的电压并确定源极线路上的第二电流，第二电流对应于响应于施加到接入线路的第二感测电压而导通的组中的第二数量的存储器单元。 设备的数量可以包括控制器，其被配置为至少部分地基于第一电流和第二电流来确定对应于该组存储器单元的Vt分布的至少一部分。
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78.发明授权公开(公告)号：US09165937B2
公开(公告)日：2015-10-20
申请号：US13932551
申请日：2013-07-01
Applicant: Micron Technology, Inc.
Inventor： Aaron Yip , Qiang Tang , Chang Wan Ha
IPC: H01L27/115
CPC classification number: H01L27/11556 , G11C16/06 , H01L27/115 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582
Abstract: Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.
Abstract translation: 诸如三维存储器件的半导体器件包括包括导电层堆叠和阶梯结构的存储器阵列。 阶梯结构位于存储器阵列的第一和第二部分之间，并且包括用于导电层叠层的相应导电层的接触区域。 存储器阵列的第一部分包括在堆叠上沿特定方向延伸的第一多个选择栅极。 存储器阵列的第二部分包括第二多个选择栅极，其也沿着导电层叠层的特定方向延伸。 还公开了形成方法和操作这种半导体器件的方法，包括垂直存储器件。
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公开(公告)号：US11733887B2
公开(公告)日：2023-08-22
申请号：US17316956
申请日：2021-05-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Luigi Pilolli , Ali Feiz Zarrin Ghalam , Guan Wang , Qiang Tang
CPC classification number: G06F3/0632 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C16/32
Abstract: A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.
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公开(公告)号：US20220359014A1
公开(公告)日：2022-11-10
申请号：US17873216
申请日：2022-07-26
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Qiang Tang , Ramin Ghodsi
Abstract: Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.
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