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    High density resistive random access memory (RRAM)
    73.
    发明授权
    High density resistive random access memory (RRAM) 有权
    高密度电阻随机存取存储器（RRAM）

    公开(公告)号：US09570512B2

    公开(公告)日：2017-02-14

    申请号：US14960595

    申请日：2015-12-07

    Applicant: STMicroelectronics, Inc.

    Inventor： Qing Liu ,  John Hongguang Zhang

    IPC: H01L21/4763 ,  H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

    Abstract: A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line.

    Abstract translation: 在支撑衬底上形成电阻随机存取存储器（RRAM）结构，并且包括第一电极和第二电极。 第一电极由支撑衬底上的硅化物翅片和覆盖硅化物翅片的第一金属衬垫层制成。 具有可配置电阻性能的电介质材料层覆盖第一金属衬垫的至少一部分。 第二电极由覆盖电介质材料层的第二金属衬垫层和与第二金属衬垫层接触的金属填充物制成。 非易失性存储单元包括电连接在存取晶体管和位线之间的RRAM结构。

    SEMI-FLOATING GATE FET
    74.
    发明申请
    SEMI-FLOATING GATE FET 有权
    半浮阀门FET

    公开(公告)号：US20160365456A1

    公开(公告)日：2016-12-15

    申请号：US14739634

    申请日：2015-06-15

    Applicant: STMicroelectronics, Inc.

    Inventor： Qing Liu ,  John H. Zhang

    IPC: H01L29/788 ,  H01L27/088 ,  H01L29/66

    CPC classification number: H01L29/7883 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7889

    Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

    Abstract translation: 半浮栅晶体管被实现为内置于硅衬底上的垂直FET，其中源极，漏极和沟道彼此垂直对准。 源极和漏极之间的电流流动受到控制栅极和半浮栅的影响。 可以对垂直半浮栅晶体管的源极，漏极和控制栅极端子中的每一个进行正面接触。 垂直半浮栅FET还包括垂直隧道FET和垂直二极管。 垂直半浮栅FET的制造与常规CMOS制造工艺兼容，包括替代金属栅极工艺。 与传统的平面器件相比，低功耗操作允许垂直半浮栅FET提供高电流密度。

    TUNNELING FIELD EFFECT TRANSISTOR (TFET) HAVING A SEMICONDUCTOR FIN STRUCTURE
    75.
    发明申请
    TUNNELING FIELD EFFECT TRANSISTOR (TFET) HAVING A SEMICONDUCTOR FIN STRUCTURE 有权
    具有半导体结构的隧道场效应晶体管（TFET）

    公开(公告)号：US20160322479A1

    公开(公告)日：2016-11-03

    申请号：US14698921

    申请日：2015-04-29

    Applicant: STMicroelectronics, Inc.

    Inventor： Qing Liu ,  Salih Muhsin Celik

    IPC: H01L29/66 ,  H01L29/06 ,  H01L29/51 ,  H01L29/165 ,  H01L29/78

    CPC classification number: H01L29/66977 ,  H01L29/0649 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/165 ,  H01L29/4941 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/7851

    Abstract: A tunneling field effect transistor is formed from a fin of semiconductor material on a support substrate. The fin of semiconductor material includes a source region, a drain region and a channel region between the source region and drain region. A gate electrode straddles over the fin at the channel region. Sidewall spacers are provided on each side of the gate electrode. The source of the transistor is made from an epitaxial germanium content source region grown from the source region of the fin and doped with a first conductivity type. The drain of the transistor is made from an epitaxial silicon content drain region grown from the drain region of the fin and doped with a second conductivity type.

    Abstract translation: 隧道场效应晶体管由支撑基板上的半导体材料的翅片形成。 半导体材料的鳍片包括源极区域，漏极区域和源极区域与漏极区域之间的沟道区域。 栅极电极横跨在通道区域上的翅片上。 在栅电极的每一侧设置侧壁间隔物。 晶体管的源极由从鳍片的源极区域生长并掺杂有第一导电类型的外延锗含量源区域制成。 晶体管的漏极由从鳍片的漏极区域生长并掺杂有第二导电类型的外延硅含量漏极区域制成。

    DUAL CHANNEL FINFET WITH RELAXED PFET REGION
    76.
    发明申请
    DUAL CHANNEL FINFET WITH RELAXED PFET REGION 有权
    具有松弛PFET区域的双通道FINFET

    公开(公告)号：US20160284607A1

    公开(公告)日：2016-09-29

    申请号：US14670800

    申请日：2015-03-27

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

    Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

    IPC: H01L21/84 ,  H01L29/78 ,  H01L27/12

    CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/7849

    Abstract: Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.

    Abstract translation: 制造半导体器件包括提供设置在电介质层上的应变半导体材料（SSM）层，在SSOI结构上形成第一多个鳍片，第一组多个鳍片中的至少一个鳍片在nFET区域中，并且至少一个 鳍状物在pFET区域中，在pFET区域中的至少一个鳍片的SSM层的部分之下蚀刻介电层的部分，通过蚀刻清除的填充区域，从至少一个鳍片形成第二多个鳍片 所述nFET区域使得每个鳍片包括设置在所述电介质层上的所述SSM层的一部分，以及从所述pFET区域中的所述至少一个翅片形成第三多个翅片，使得每个翅片包括设置在所述SSM层上的部分 可流动的氧化物。

    MACRO TO MONITOR N-P BUMP
    77.
    发明申请
    MACRO TO MONITOR N-P BUMP 有权
    宏观监控N-P BUMP

    公开(公告)号：US20160284602A1

    公开(公告)日：2016-09-29

    申请号：US14669055

    申请日：2015-03-26

    Applicant: International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

    Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

    IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/308 ,  H01L21/66 ,  H01L21/768

    CPC classification number: H01L21/823871 ,  H01L21/30625 ,  H01L21/3085 ,  H01L21/82385 ,  H01L22/12 ,  H01L22/30

    Abstract: A technique relates to fabricating a macro for measurements utilized in dual spacer, dual epitaxial transistor devices. The macro is fabricated according to a fabrication process. The macro is a test layout of a semiconductor structure having n-p bumps at junctions between NFET areas and PFET areas. Optical critical dimension (OCD) spectroscopy is performed to obtain the measurements of the n-p bumps on the macro. An amount of chemical mechanical polishing is determined to remove the n-p bumps on the macro based on the measurements of the n-p bumps on the macro. Chemical mechanical polishing is performed to remove the n-p bumps on the macro. The amount previously determined for the macro is utilized to perform chemical mechanical polishing for each of the dual spacer, dual epitaxial layer transistor devices having been fabricated under the fabrication process of the macro in which the fabrication process produced the n-p bumps.

    Abstract translation: 技术涉及制造用于双间隔物，双外延晶体管器件中的测量的宏。 宏是根据制造工艺制造的。 该宏是在NFET区域和PFET区域之间的结处具有n-p个凸起的半导体结构的测试布局。 执行光临界尺度（OCD）光谱以获得宏观上的n-p凸块的测量。 基于宏观上的n-p凸块的测量，确定了一定量的化学机械抛光以去除宏观上的n-p凸块。 进行化学机械抛光以除去宏观上的n-p凸块。 先前为宏确定的量用于对在制造工艺产生n-p个凸块的宏的制造过程中制造的每个双间隔物，双外延层晶体管器件进行化学机械抛光。

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