公开(公告)号：US20050083757A1

公开(公告)日：2005-04-21

申请号：US10971204

申请日：2004-10-21

申请人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

发明人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

IPC分类号： G11C11/15 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24 ,  G11C7/00

CPC分类号： G11C11/15 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/72 ,  H01L27/24

摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

摘要翻译： 提供了电阻式交叉点存储器件，以及制造和使用方法。 存储器件由介于上电极和下电极之间的电阻存储器材料的有源层组成。 在上电极和下电极的交叉点处位于电阻性存储器材料内的位区域具有响应于施加一个或更多个电压脉冲而能够在一定范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。 在电阻性存储器材料和下电极之间的界面处形成二极管，其可以形成为掺杂区域。 电阻交叉点存储器件通过在衬底内掺杂一行极性形成，然后将相反极性的线的掺杂区域形成二极管。 然后在二极管上形成一层电阻记忆材料覆盖底部电极的底部电极。 然后可以以倾斜的角度添加顶部电极以形成由线和顶部电极限定的交叉点阵列。

公开(公告)号：US20050079727A1

公开(公告)日：2005-04-14

申请号：US10677008

申请日：2003-09-30

申请人： Fengyan Zhang ,  Sheng Hsu

发明人： Fengyan Zhang ,  Sheng Hsu

IPC分类号： H01L21/28 ,  G11C13/00 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L45/00 ,  H01L21/302 ,  H01L21/461

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L21/31122 ,  H01L21/32136 ,  H01L27/101 ,  H01L28/55 ,  H01L28/65 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

摘要： A method of dry etching a PCMO stack, includes preparing a substrate; depositing a barrier layer; depositing a bottom electrode; depositing a PCMO thin film; depositing a top electrode; depositing a hard mask layer; applying photoresist and patterning; etching the hard mask layer; dry etching the top electrode; dry etching the PCMO layer in a multi-step etching process; dry etching the bottom electrode; and completing the PCMO-based device.

摘要翻译： 一种干法蚀刻PCMO堆叠的方法，包括制备衬底; 沉积阻挡层; 沉积底部电极; 沉积PCMO薄膜; 沉积顶部电极; 沉积硬掩模层; 应用光刻胶和图案化; 蚀刻硬掩模层; 干法蚀刻顶部电极; 在多步蚀刻工艺中干法刻蚀PCMO层; 干蚀下层电极; 并完成基于PCMO的设备。

公开(公告)号：US20050003663A1

公开(公告)日：2005-01-06

申请号：US10903610

申请日：2004-07-29

申请人： Wei Pan ,  Jer-Shen Maa ,  David Evans ,  Sheng Hsu

发明人： Wei Pan ,  Jer-Shen Maa ,  David Evans ,  Sheng Hsu

IPC分类号： H01L21/3205 ,  C23C16/02 ,  C23C16/18 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76843 ,  C23C16/0209 ,  C23C16/18 ,  H01L21/28556 ,  H01L21/76864 ,  H01L21/76876

摘要： A rapid thermal process (RTP) provides steps wherein silicon wafers that are pre-coated with barrier metal films by either in-situ or ex-situ CVD or physical vapor deposition (PVD) are pre-treated, prior to deposition of a Cu film thereon, in a temperature range of between 250 and 550 degrees Celsius in a non-reactive gas such as hHydrogen gas (H2), argon (Ar), or helium (He), or in an ambient vacuum. The chamber pressure typically is between 0.1 mTorr and 20 Torr, and the RTP time typically is between 30 to 100 seconds. Performing this rapid thermal process before deposition of the Cu film results in a thin, shiny, densely nucleated, and adhesive Cu film deposited on a variety of barrier metal surfaces. The pre-treatment process eliminates variations in the deposited Cu film caused by Cu precursors and is insensitive to variation in precursor composition, volatility, and other precursor variables. Accordingly, the process disclosed herein is an enabling technology for the use of metal organic CVD (MOCVD) Cu in IC fabrication.

摘要翻译： 快速热处理（RTP）提供了在沉积Cu膜之前预处理通过原位或原位CVD或物理气相沉积（PVD）预涂覆有阻挡金属膜的硅晶片的步骤 在非反应性气体例如氢气（H 2），氩气（Ar）或氦气（He）中，或在环境真空中，在250-550℃的温度范围内。 室压力通常在0.1mTorr和20Torr之间，并且RTP时间通常在30至100秒之间。 在沉积Cu膜之前进行这种快速热处理会导致沉积在各种阻挡金属表面上的薄而有光泽，致密成核和粘附的Cu膜。 预处理过程消除了由Cu前体引起的沉积的Cu膜的变化，并且对前体组成，挥发性和其它前体变量的变化不敏感。 因此，本文公开的方法是在IC制造中使用金属有机CVD（MOCVD）Cu的使能技术。

公开(公告)号：US20090309504A1

公开(公告)日：2009-12-17

申请号：US12139287

申请日：2008-06-13

申请人： Sheng Hsu

发明人： Sheng Hsu

IPC分类号： H05B37/02

CPC分类号： H05B33/0842 ,  H05B33/0803 ,  H05B33/0857 ,  H05B33/0863

摘要： A color-controllable light string has a control box and a light string composed of lighting units. The control box provides a DC power to the lighting units through two power wires and transmits a synchronization signal to the lighting units through a signal wire. Each of the lighting units has a waterproof assembly constructing a sealed environment and an LED circuit board with multiple LEDs of different colors mounted in the sealed environment to provide colorful lights by mixing and activating proper LEDs.

摘要翻译： 颜色可控的灯串具有控制箱和由照明单元组成的灯串。 控制箱通过两根电源线为照明装置提供直流电源，并通过信号线将同步信号发送到照明装置。 每个照明单元具有构造密封环境的防水组件和安装在密封环境中的具有不同颜色的多个LED的LED电路板，以通过混合和激活适当的LED来提供彩色光。

公开(公告)号：US20070109835A1

公开(公告)日：2007-05-17

申请号：US11283135

申请日：2005-11-17

申请人： Sheng Hsu

发明人： Sheng Hsu

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  G11C13/0023 ,  G11C13/004 ,  G11C2213/77

摘要： A cross-point RRAM memory array includes a word line array having an array of substantially parallel word lines therein and a bit line array having an array of substantially parallel bit lines therein, wherein said bit lines are substantially perpendicular to said word lines, and wherein a cross-point is formed between said word lines and said bit lines. A memory resistor located between said word lines and said bit lines at each cross-point. A high-open-circuit-voltage gain, bit line sensing differential amplifier circuit located on each bit line, including a feedback resistor and a high-open-circuit-voltage gain amplifier, arranged in parallel, wherein a resistance of the feedback resistors is greater than a resistance of any of the memory resistors programmed at a low resistance state.

公开(公告)号：US20070045694A1

公开(公告)日：2007-03-01

申请号：US11215484

申请日：2005-08-30

申请人： Sheng Hsu

发明人： Sheng Hsu

IPC分类号： H01L29/76

CPC分类号： H01L45/1253 ,  G11C13/00 ,  G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method of determining a memory material and an associated electrode material for use in a RRAM device includes selecting a memory material having an inner orbital having less than a full quota of electrons and a narrow, outer conductive orbital; and selecting an associated electrode material for injecting a packet of electrons into the selected memory material when subjected to a narrow-width electric pulse, and which recovers the packet of electrons when subjected to a large-width electric pulse.

摘要翻译： 一种确定用于RRAM设备的存储材料和相关电极材料的方法包括选择具有小于全部电子配额的内轨道和窄的外导电轨道的存储材料; 以及当经受窄宽电脉冲时选择用于将电子包注入所选择的存储材料中的相关联的电极材料，并且当经受大宽度电脉冲时，电子包回收。

公开(公告)号：US20070015329A1

公开(公告)日：2007-01-18

申请号：US11216398

申请日：2005-08-31

申请人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang ,  David Evans

发明人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang ,  David Evans

IPC分类号： H01L21/8242

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method comprises: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

摘要翻译： 提供了一种用于形成具有MSM限流器的金属/半导体/金属（MSM）限流器和电阻存储器单元的方法。 该方法包括：提供衬底; 形成覆盖所述衬底的MSM底部电极; 形成覆盖MSM底部电极的ZnO x半导体层，其中x在约1和约2之间的范围内; 并且形成覆盖半导体层的MSM顶部电极。 可以通过旋涂，直流（DC）溅射，射频（RF）溅射，金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）等多种不同的工艺形成ZnO x半导体。

公开(公告)号：US20070010037A1

公开(公告)日：2007-01-11

申请号：US11175797

申请日：2005-07-05

申请人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang

发明人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang

IPC分类号： H01L21/00

CPC分类号： H01L33/34 ,  B82Y20/00 ,  H01L33/0012

摘要： A superlattice nanocrystal Si—SiO2 electroluminescence (EL) device and fabrication method have been provided. The method comprises: providing a Si substrate; forming an initial SiO2 layer overlying the Si substrate; forming an initial polysilicon layer overlying the initial SiO2 layer; forming SiO2 layer overlying the initial polysilicon layer; repeating the polysilicon and SiO2 layer formation, forming a superlattice; doping the superlattice with a rare earth element; depositing an electrode overlying the doped superlattice; and, forming an EL device. In one aspect, the polysilicon layers are formed by using a chemical vapor deposition (CVD) process to deposit an amorphous silicon layer, and annealing. Alternately, a DC-sputtering process deposits each amorphous silicon layer, and following the forming of the superlattice, polysilicon is formed by annealing the amorphous silicon layers. Silicon dioxide can be formed by either thermal annealing or by deposition using a DC-sputtering process.

摘要翻译： 已经提供了超晶格纳米晶Si-SiO 2电致发光（EL）器件及其制造方法。 该方法包括：提供Si衬底; 形成覆盖Si衬底的初始SiO 2层; 形成覆盖初始SiO 2层的初始多晶硅层; 形成覆盖在初始多晶硅层上的SiO 2层; 重复多晶硅和SiO 2层形成，形成超晶格; 用稀土元素掺杂超晶格; 沉积覆盖掺杂超晶格的电极; 并且形成EL器件。 在一个方面，通过使用化学气相沉积（CVD）工艺沉积非晶硅层和退火来形成多晶硅层。 或者，DC溅射工艺沉积每个非晶硅层，并且在形成超晶格之后，通过退火非晶硅层形成多晶硅。 可以通过热退火或通过使用DC溅射工艺的沉积来形成二氧化硅。

公开(公告)号：US20070004226A1

公开(公告)日：2007-01-04

申请号：US11174350

申请日：2005-07-01

申请人： Douglas Tweet ,  Yoshi Ono ,  David Evans ,  Sheng Hsu

发明人： Douglas Tweet ,  Yoshi Ono ,  David Evans ,  Sheng Hsu

IPC分类号： H01L21/31

CPC分类号： H01L21/02192 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/3147

摘要： A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.

摘要翻译： 一种控制单晶外延氧化膜中的应变的方法包括制备硅衬底; 从由Si 1-x Ge x Si和Si 1-y C C组成的硅合金层组形成硅合金层 > y ; 通过选择合金材料含量来调整硅合金层的晶格常数，并选择一种用于硅合金层的应变; 从由不含锰的钙钛矿亚锰酸盐材料，单晶稀土氧化物和钙钛矿氧化物组成的氧化膜组中，通过原子层沉积法沉积单晶外延氧化膜; 和稀土二元和三元氧化物，在硅合金层上; 并完成所需的设备。

公开(公告)号：US20060160304A1

公开(公告)日：2006-07-20

申请号：US11039544

申请日：2005-01-19

申请人： Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

发明人： Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

IPC分类号： H01L21/336

CPC分类号： H01L27/101 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1675

摘要： A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.

摘要翻译： 提供了具有纳米尖端电极的非易失性存储器电阻单元及相应的制造方法。 该方法包括：形成具有纳米尖端的第一电极; 在所述纳米尖端附近形成记忆电阻材料; 并且形成与所述存储电阻材料相邻的第二电极，其中所述存储电阻材料置于所述第一和第二电极之间。 通常，纳米针是氧化铱（IrOx），并且具有约50纳米或更小的尖端基底尺寸，在5至50nm范围内的尖端高度，以及每平方微米大于100纳米尖端的纳米密度密度。 一方面，衬底材料可以是硅，氧化硅，氮化硅或贵金属。 使用金属有机化学气相沉积（MOCVD）工艺沉积Ir。 IrOx纳米尖端从沉积的Ir生长。