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    Method of synthesis of hafnium nitrate for HfO2 thin film deposition via ALCVD process
    71.
    发明授权
    Method of synthesis of hafnium nitrate for HfO2 thin film deposition via ALCVD process 失效
    通过ALCVD法合成HfO2薄膜沉积硝酸铪的方法

    公开(公告)号：US06899858B2

    公开(公告)日：2005-05-31

    申请号：US10350641

    申请日：2003-01-23

    申请人： Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

    发明人： Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

    IPC分类号： C01G27/00 ,  C01G27/02 ,  C23C16/40 ,  H01L21/316 ,  C01B21/48

    CPC分类号： C01G27/00 ,  C01G27/02

    摘要： A method of preparing a hafnium nitrate thin film includes placing phosphorus pentoxide in a first vessel; connecting the first vessel to a second vessel containing hafnium tetrachloride; cooling the second vessel with liquid nitrogen; dropping fuming nitric acid into the first vessel producing N2O5 gas; allowing the N2O5 gas to enter the second vessel; heating the first vessel until the reaction is substantially complete; disconnecting the two vessels; removing the second vessel from the liquid nitrogen bath; heating the second vessel; refluxing the contents of the second vessel; drying the compound in the second vessel by dynamic pumping; purifying the compound in the second vessel by sublimation to form Hf(NO3)4, and heating the Hf(NO3)4 to produce HfO2 for use in an ALCVD process.

    摘要翻译： 制备硝酸铪薄膜的方法包括将五氧化二磷放置在第一容器中; 将第一容器连接到含有四氯化铪的第二容器; 用液氮冷却第二个容器; 将发烟硝酸滴入产生N 2 O 5气体的第一容器中; 允许N 2 O 5气体进入第二容器; 加热第一个容器直到反应基本完成; 断开两艘船舶; 从液氮浴中除去第二容器; 加热第二艘船; 回流第二容器的内容物; 通过动态泵送干燥第二容器中的化合物; 通过升华纯化第二容器中的化合物以形成Hf（NO 3 N 3）4，并加热Hf（NO 3 N 3）3 4生产用于ALCVD工艺的HfO 2 2。

    Alkene ligand precursor and synthesis method
    73.
    发明授权
    Alkene ligand precursor and synthesis method 有权
    烯配体前体和合成方法

    公开(公告)号：US6090963A

    公开(公告)日：2000-07-18

    申请号：US281722

    申请日：1999-03-30

    申请人： Wei-Wei Zhuang ,  Tue Nguyen ,  Robert Barrowcliff ,  David Russell Evans ,  Sheng Teng Hsu

    发明人： Wei-Wei Zhuang ,  Tue Nguyen ,  Robert Barrowcliff ,  David Russell Evans ,  Sheng Teng Hsu

    IPC分类号： C07C11/02 ,  C07C49/92 ,  C07F1/08 ,  C23C16/18

    CPC分类号： C23C16/18

    摘要： A metal(hfac), alkene ligand precursor has been provided. The alkene ligand includes double bonded carbon atoms, with first and second bonds to the first carbon atom, and third and fourth bonds to the second carbon atom. The first, second, third, and fourth bonds are selected from a the group consisting of H, C.sub.1 to C.sub.8 alkyl, C.sub.1 to C.sub.8 haloalkyl, and C.sub.1 to C.sub.8 alkoxyl. As a general class, these precursors are capable of high metal deposition rates and high volatility, despite being stable in the liquid phase at low temperatures. Copper deposited with this precursor has low resistivity and high adhesive characteristics. A synthesis method has been provided which produces a high yield of the above-described alkene ligand class of metal precursors.

    摘要翻译： 已经提供了金属（hfac），烯烃配体前体。 烯属配体包括双键键合的碳原子，与第一个碳原子具有第一个和第二个键，第三个和第四个键连接到第二个碳原子。 第一，第二，第三和第四键选自H，C 1至C 8烷基，C 1至C 8卤代烷基和C 1至C 8烷氧基。 作为一般类别，尽管在低温下在液相中稳定，但这些前体能够具有高的金属沉积速率和高挥发性。 沉积有该前体的铜具有低电阻率和高粘合特性。 已经提供了产生上述烯属配体类金属前体的高产率的合成方法。

    Self-aligned cross point resistor memory array
    74.
    发明授权
    Self-aligned cross point resistor memory array 有权
    自对准交叉点电阻存储器阵列

    公开(公告)号：US07323349B2

    公开(公告)日：2008-01-29

    申请号：US11120385

    申请日：2005-05-02

    申请人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Wei-Wei Zhuang

    发明人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Wei-Wei Zhuang

    IPC分类号： H01L21/00 ,  H01L21/8242

    CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1683

    摘要： A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.

    摘要翻译： 制造电阻器存储器阵列的方法包括制备硅衬底; 在衬底P +层上沉积底部电极，牺牲层和硬掩模层; 掩模，图案化和蚀刻以在第一方向上去除硬掩模，牺牲材料，底部电极的一部分; 沉积一层氧化硅; 掩模，图案化和蚀刻以在垂直于第一方向的第二方向上去除硬掩模，牺牲材料，底部电极的一部分，并且对N +层和至少100nm的硅衬底进行过蚀刻 ; 沉积一层氧化硅; 蚀刻以除去任何剩余的硬掩模和任何剩余的牺牲材料; 沉积一层CMR材料; 沉积顶部电极; 施加光致抗蚀剂，图案化光致抗蚀剂并蚀刻顶部电极; 并将存储器阵列并入集成电路中。

    Low cross-talk electrically programmable resistance cross point memory
    75.
    发明授权
    Low cross-talk electrically programmable resistance cross point memory 有权
    低串扰电可编程电阻交叉点存储器

    公开(公告)号：US06693821B2

    公开(公告)日：2004-02-17

    申请号：US09893830

    申请日：2001-06-28

    申请人： Sheng Teng Hsu ,  Wei-Wei Zhuang

    发明人： Sheng Teng Hsu ,  Wei-Wei Zhuang

    IPC分类号： G11C1100

    CPC分类号： H01L27/24 ,  G11C11/15 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/77

    摘要： Low cross talk resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises a bit formed using a perovskite material interposed at a cross point of an upper electrode and lower electrode. Each bit has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit, decrease the resistivity of the bit, or determine the resistivity of the bit. Memory circuits are provided to aid in the programming and read out of the bit region.

    摘要翻译： 提供了低串扰电阻交叉点存储器件，以及制造和使用方法。 存储装置包括使用插入在上电极和下电极的交叉点处的钙钛矿材料形成的钻头。 每个位具有响应于施加一个或多个电压脉冲而可以在一定范围内的值改变的电阻率。 可以使用电压脉冲来增加比特的电阻率，降低比特的电阻率或确定比特的电阻率。 提供存储器电路以帮助编程和读出位区域。

    Method of fabricating 1T1R resistive memory array
    76.
    发明授权
    Method of fabricating 1T1R resistive memory array 有权
    制造1T1R电阻式存储器阵列的方法

    公开(公告)号：US06583003B1

    公开(公告)日：2003-06-24

    申请号：US10256362

    申请日：2002-09-26

    申请人： Sheng Teng Hsu ,  Wei-Wei Zhuang

    发明人： Sheng Teng Hsu ,  Wei-Wei Zhuang

    IPC分类号： H01L218242

    CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

    摘要： A method is provided for forming a 1T1R resistive memory array. The method of forming a 1T1R resistive memory array structure on a semiconductor substrate comprises forming an array of transistors comprising a polycide/oxide/nitride gate stack with nitride sidewalls, the transistors comprising a source and a drain region adjacent to the gate stack. An insulating layer is deposited and planarized level with the polycide/oxide/nitride gate stack. Bit contact openings are etched to expose the drain region. Bottom electrodes are formed by depositing and planarizing a metal. A resistive memory material is deposited over the bottom electrodes. Top electrodes are formed over the resistive memory material. The 1T1R resistive memory array may be connected to support circuits that are formed on the same substrate as the memory array. The support circuits may share many of the process steps with the formation of the transistors for the memory array.

    摘要翻译： 提供了一种用于形成1T1R电阻式存储器阵列的方法。 在半导体衬底上形成1T1R电阻性存储器阵列结构的方法包括形成包括具有氮化物侧壁的多晶硅/氧化物/氮化物栅叠层的晶体管阵列，所述晶体管包括与栅叠层相邻的源区和漏区。 绝缘层与多晶硅/氧化物/氮化物栅极叠层沉积并平坦化。 蚀刻位触点开口以露出漏极区域。 通过沉积和平坦化金属形成底部电极。 电阻性记忆材料沉积在底部电极上。 顶部电极形成在电阻式存储器材料上。 1T1R电阻式存储器阵列可以连接到形成在与存储器阵列相同的衬底上的支撑电路。 支持电路可以与存储器阵列的晶体管的形成共享许多处理步骤。

    Substituted ethylene precursor and synthesis method
    78.
    发明授权
    Substituted ethylene precursor and synthesis method 有权
    取代乙烯前体及其合成方法

    公开(公告)号：US5994571A

    公开(公告)日：1999-11-30

    申请号：US215921

    申请日：1998-12-18

    申请人： Wei-Wei Zhuang ,  Tue Nguyen ,  Lawrence J. Charneski ,  David Russell Evans ,  Sheng Teng Hsu

    发明人： Wei-Wei Zhuang ,  Tue Nguyen ,  Lawrence J. Charneski ,  David Russell Evans ,  Sheng Teng Hsu

    IPC分类号： C07C11/04 ,  C07F1/08 ,  C07F1/10 ,  C07F15/00 ,  C23C16/18 ,  H01L21/285 ,  C23C16/00

    CPC分类号： C23C16/18 ,  C07F1/08

    摘要： A Cu(hfac) precursor with a substituted ethylene ligand has been provided. The substituted ethylene ligand includes bonds to molecules selected from the group consisting of C.sub.1 to C.sub.8 alkyl, C.sub.1 to C.sub.8 haloalkyl, H, and C.sub.1 to C.sub.8 alkoxyl. One variation, the 2-methyl-1-butene ligand precursor has proved to be stable at room temperature, and extremely volatile at higher temperatures. Copper deposited with this precursor has low resistivity and high adhesive characteristics. Because of the volatility, the deposition rate of copper deposited with this precursor is very high. A synthesis method has been provided which produces a high yield of the above-described precursor.

    摘要翻译： 已经提供了具有取代的乙烯配体的Cu（hfac）前体。 取代的乙烯配体包括与选自C1至C8烷基，C1至C8卤代烷基，H和C1至C8烷氧基的分子的键。 一个变体，2-甲基-1-丁烯配体前体已被证明在室温下是稳定的，并且在较高温度下极易挥发。 沉积有该前体的铜具有低电阻率和高粘合特性。 由于挥发性，沉积有这种前体的铜的沉积速率非常高。 已经提供了产生高产率的上述前体的合成方法。

    Device and method for reversible resistance change induced by electric pulses in non-crystalline perovskite unipolar programmable memory
    80.
    发明授权
    Device and method for reversible resistance change induced by electric pulses in non-crystalline perovskite unipolar programmable memory 有权
    在非晶体钙钛矿单极可编程存储器中由电脉冲引起的可逆电阻变化的装置和方法

    公开(公告)号：US06759249B2

    公开(公告)日：2004-07-06

    申请号：US10072225

    申请日：2002-02-07

    申请人： Wei-Wei Zhuang ,  Sheng Teng Hsu

    发明人： Wei-Wei Zhuang ,  Sheng Teng Hsu

    IPC分类号： H01L2100

    CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  Y10S502/525

    摘要： A method of fabricating a variable resistance device, wherein the resistance is changed by passing a voltage of various pulse length through the device, includes preparing a silicon substrate; forming a silicon oxide layer on the substrate; depositing a first metal layer on the silicon oxide, wherein the metal of the first metal layer is taken from the group of metals consisting of platinum and iridium; depositing a perovskite metal oxide thin film on the first metal layer; depositing a second metal layer on the perovskite metal oxide, wherein the metal of the second metal layer is taken from the group of metals consisting of platinum and iridium; annealing the structure at a temperature of between about 400° C. to 700° C. for between about five minutes and three hours; and completing the variable resistance device. A variable resistance R-RAM device includes a silicon substrate having a silicon oxide layer thereon; a first metal layer formed on the silicon oxide layer, wherein the metal of the first metal layer is taken from the group of metals consisting of platinum and iridium; a perovskite metal oxide thin film layer formed on the first metal layer; a second metal layer formed on the perovskite metal oxide, wherein the metal of the second metal layer is taken from the group of metals consisting of platinum and iridium; and metallizing elements to provide a complete device.

    摘要翻译： 一种制造可变电阻器件的方法，其中通过使各种脉冲长度的电压通过器件来改变电阻，包括制备硅衬底; 在所述基板上形成氧化硅层; 在所述氧化硅上沉积第一金属层，其中所述第一金属层的金属取自由铂和铱组成的金属组; 在第一金属层上沉积钙钛矿金属氧化物薄膜; 在所述钙钛矿金属氧化物上沉积第二金属层，其中所述第二金属层的金属取自由铂和铱组成的金属组; 在约400℃至700℃的温度下退火结构约5分钟至3小时; 并完成可变电阻装置。 可变电阻R-RAM器件包括其上具有氧化硅层的硅衬底; 形成在所述氧化硅层上的第一金属层，其中所述第一金属层的金属取自由铂和铱组成的金属组; 形成在所述第一金属层上的钙钛矿金属氧化物薄膜层; 形成在钙钛矿金属氧化物上的第二金属层，其中第二金属层的金属取自由铂和铱组成的金属组; 和金属化元件以提供完整的装置。