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公开(公告)号：US07183795B2
公开(公告)日：2007-02-27
申请号：US10947765
申请日：2004-09-23
申请人： Yibin Ye , James W. Tschanz , Muhammad M. Khellah , Vivek K. De
发明人： Yibin Ye , James W. Tschanz , Muhammad M. Khellah , Vivek K. De
IPC分类号： H03K19/23
CPC分类号： H03K19/23
摘要： Apparatus and systems, as well as methods and articles, may operate to provide a majority voter indication using a sense amplifier coupled to a first plurality of bit inputs and to a second plurality of bit inputs.
摘要翻译： 装置和系统以及方法和物品可以使用耦合到第一多个位输入和第二多个位输入的读出放大器来提供多数选举指示。
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公开(公告)号：US07020041B2
公开(公告)日：2006-03-28
申请号：US10738216
申请日：2003-12-18
申请人： Dinesh Somasekhar , Muhammad M. Khellah , Yibin Ye , Vivek K. De , James W. Tschanz , Stephen H. Tang
发明人： Dinesh Somasekhar , Muhammad M. Khellah , Yibin Ye , Vivek K. De , James W. Tschanz , Stephen H. Tang
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C5/147 , G11C11/413
摘要： An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.
摘要翻译： 提供了一种用于限制SRAM装置中的电源电压下降以保持IDLE状态期间存储器的状态的装置和方法。 该装置可以包括存储器阵列，睡眠装置和钳位电路。 钳位电路可以被配置为当存储器阵列上的电压降低于预设电压并且存储器阵列处于空闲状态时激活睡眠装置。
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73.发明授权Resilient register file circuit for dynamic variation tolerance and method of operating the same 有权用于动态变化公差的弹性寄存器文件电路及其操作方法公开(公告)号：US09329918B2
公开(公告)日：2016-05-03
申请号：US13976859
申请日：2011-12-28
CPC分类号： G06F11/1068 , G06F9/30141 , G06F9/3861 , G06F11/0751 , G06F11/1008 , G11C7/18 , G11C29/42 , G11C29/52
摘要： The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.
摘要翻译： 所公开的系统和方法检测并校正由于减少或消除CPU的电源电压保护带和/或频率保护带而可能发生的寄存器文件读取路径错误，从而提高系统的总体能量效率。
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公开(公告)号：US09230636B2
公开(公告)日：2016-01-05
申请号：US14137808
申请日：2013-12-20
申请人： Pascal A. Meinerzhagen , Jaydeep P. Kulkarni , Muhammad M. Khellah , Cyrille Dray , Dinesh Somasekhar , James W. Tschanz , Vivek K. De
发明人： Pascal A. Meinerzhagen , Jaydeep P. Kulkarni , Muhammad M. Khellah , Cyrille Dray , Dinesh Somasekhar , James W. Tschanz , Vivek K. De
IPC分类号： G11C5/14 , G11C11/4074 , G11C11/16 , G11C16/06 , G11C11/406 , G11C11/4076 , G11C5/06 , G11C11/408
CPC分类号： G11C11/4074 , G11C5/063 , G11C5/14 , G11C5/145 , G11C5/148 , G11C11/1697 , G11C11/406 , G11C11/4076 , G11C11/4085 , G11C11/4087 , G11C11/417 , G11C16/06
摘要： Described is an apparatus which comprises: a first power supply node to provide a first power supply, a second power supply node, and a third power supply node; a first transistor which is operable to couple the first and second power supply nodes; and a charge pump circuit to provide a boosted voltage to the third power supply node in one mode, and to recover charge from the second power node in another mode. Described is a memory unit which comprises: a DRAM which is operable to be refreshed; a gated power supply node coupled to the DRAM to provide a gated power supply to the DRAM; and a charge recycling circuit to recover charge from the gated power supply node after the DRAM is refreshed.
摘要翻译： 描述了一种装置，包括：提供第一电源的第一电源节点，第二电源节点和第三电源节点; 第一晶体管，其可操作以耦合所述第一和第二电源节点; 以及电荷泵电路，以一种模式向第三电源节点提供升压电压，并且在另一模式下从第二功率节点恢复电荷。 描述了一种存储单元，其包括：可操作以刷新的DRAM; 门极电源节点，其耦合到DRAM以向DRAM提供门控电源; 以及充电回收电路，用于在DRAM被刷新之后从门控电源节点恢复电荷。
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公开(公告)号：US09189014B2
公开(公告)日：2015-11-17
申请号：US13664153
申请日：2012-10-30
申请人： Keith A. Bowman , James W. Tschanz , Nam Sung Kim , Janice C. Lee , Christopher B. Wilkerson , Shih-Lien L. Lu , Tanay Karnik , Vivek K. De
发明人： Keith A. Bowman , James W. Tschanz , Nam Sung Kim , Janice C. Lee , Christopher B. Wilkerson , Shih-Lien L. Lu , Tanay Karnik , Vivek K. De
IPC分类号： G06F11/07 , G06F1/08 , G06F1/10 , H03K3/037 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/31723 , G01R31/31725 , G01R31/31727 , G06F1/10 , G06F11/0706 , G06F11/0757 , G06F11/0793 , H03K3/0375
摘要： Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
摘要翻译： 提供了具有错误检测的顺序电路。 例如，它们可以用于替代传统的主从触发器，例如在关键路径电路中，以检测并启动在顺序输入处的后期转换的校正。 在一些实施例中，这样的顺序可以包括具有时间借用锁存器的转换检测器。
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公开(公告)号：US09153304B2
公开(公告)日：2015-10-06
申请号：US13536521
申请日：2012-06-28
申请人： Jaydeep P. Kulkarni , Muhammad M. Khellah , James W. Tschanz , Bibiche M. Geuskens , Vivek K. De
发明人： Jaydeep P. Kulkarni , Muhammad M. Khellah , James W. Tschanz , Bibiche M. Geuskens , Vivek K. De
IPC分类号： G11C11/00 , G11C7/22 , G11C11/419 , G11C11/412 , G11C11/413
CPC分类号： G11C11/419 , G11C7/227 , G11C11/412 , G11C11/413
摘要： Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.
摘要翻译： 描述了一种用于存储元件的写入最小电源电压的自感应降低的装置。 该装置包括：具有耦合到第一电源节点的交叉耦合的反相器的存储元件; 耦合到第一电源节点和第二电源节点的电源设备，第二电源节点耦合到电源; 以及具有耦合到字线的栅极端子，耦合到存储器元件的第一端子和耦合到位线的第二端子的存取装置，该位线可操作以在写入之前预放电到逻辑低电平 操作。
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公开(公告)号：US07109776B2
公开(公告)日：2006-09-19
申请号：US10947869
申请日：2004-09-23
申请人： James W. Tschanz , Dinesh Somasekhar , Vivek K. De
发明人： James W. Tschanz , Dinesh Somasekhar , Vivek K. De
IPC分类号： H03K3/013
CPC分类号： G06F1/10
摘要： Some embodiments provide reception of a clock signal, reception of a gating signal, and output of a gated clock signal to a dual edge-triggered-clocked circuit. The gated clock signal is based on the clock signal and on the gating signal.
摘要翻译： 一些实施例提供时钟信号的接收，门控信号的接收以及门控时钟信号输出到双边沿触发时钟电路。 门控时钟信号基于时钟信号和门控信号。
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公开(公告)号：US06992603B2
公开(公告)日：2006-01-31
申请号：US10813084
申请日：2004-03-31
申请人： Maged M. Ghoneima , Peter Caputa , Muhammad M. Khellah , Ram Krishnamurthy , James W. Tschanz , Yiben Ye , Vivek K. De , Yehea I Ismail
发明人： Maged M. Ghoneima , Peter Caputa , Muhammad M. Khellah , Ram Krishnamurthy , James W. Tschanz , Yiben Ye , Vivek K. De , Yehea I Ismail
IPC分类号： H03M7/00
CPC分类号： G06F13/4072 , Y02D10/14 , Y02D10/151
摘要： An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
摘要翻译： 提供互连架构以降低功耗。 第一驱动器可以在第一互连上驱动信号，并且第二驱动器可以在第二互连上驱动信号。 第一驱动器可以由第一电压供电，并且第二驱动器可以由不同于第一电压的第二电压供电。
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公开(公告)号：US06970018B2
公开(公告)日：2005-11-29
申请号：US10873243
申请日：2004-06-23
申请人： Dejan Markovic , James W. Tschanz , Vivek K. De
发明人： Dejan Markovic , James W. Tschanz , Vivek K. De
IPC分类号： H03K3/012 , H03K3/037 , H03K3/356 , H03K19/094
CPC分类号： H03K3/356113 , H03K3/012 , H03K3/037 , H03K3/356156
摘要： A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.
摘要翻译： 循环锁存器包括控制电路，其通过在交叉耦合的逆变器保持器结构中有条件地排放反馈节点来增加存储节点的上拉率。 周期锁存器包括用于将输入值传送到存储节点的NMOS晶体管开关和串联连接的两个NMOS晶体管，用于执行控制电路的功能。 通过将存储节点连接到预放电反馈节点，然后用低摆频时钟驱动锁存器，实现延迟时间，能量消耗和鲁棒性方面的改进的性能。
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公开(公告)号：US06806739B2
公开(公告)日：2004-10-19
申请号：US10330544
申请日：2002-12-30
申请人： Dejan Markovic , James W. Tschanz , Vivek K. De
发明人： Dejan Markovic , James W. Tschanz , Vivek K. De
IPC分类号： H03K19094
CPC分类号： H03K3/356113 , H03K3/012 , H03K3/037 , H03K3/356156
摘要： A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.
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