公开(公告)号：US10553533B2

公开(公告)日：2020-02-04

申请号：US15965978

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu ,  Nan-Chin Chuang

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/528 ,  H01L23/00

Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.

公开(公告)号：US20190371694A1

公开(公告)日：2019-12-05

申请号：US15992196

申请日：2018-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Ching-Feng Yang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Yi-Che Chiang

IPC: H01L23/367 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/538

Abstract: Semiconductor packages and methods of forming the same are provided. One of the semiconductor package includes a first die, a dummy die, a first redistribution layer structure, an insulating layer and an insulating layer. The dummy die is disposed aside the first die. The first redistribution layer structure is electrically connected to the first die and having connectors thereover. The insulating layer is disposed over the first die and the dummy die and opposite to the first redistribution layer structure. The insulating layer penetrates through the insulating layer.

公开(公告)号：US20190139890A1

公开(公告)日：2019-05-09

申请号：US15965978

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu ,  Nan-Chin Chuang

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/528 ,  H01L23/00

Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.

公开(公告)号：US10276404B2

公开(公告)日：2019-04-30

申请号：US15690300

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chung-Hao Tsai ,  Chun-Lin Lu ,  Yen-Ping Wang ,  Che-Wei Hsu

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L21/768

Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The second redistribution structure is disposed on the die and the insulation encapsulation. At least one of the first redistribution structure and the second redistribution structure includes a dielectric layer, a feed line, and a signal enhancement layer. The feed line is at least partially disposed on the dielectric layer. The signal enhancement layer covers the feed line. The signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer.

公开(公告)号：US10163824B2

公开(公告)日：2018-12-25

申请号：US15367196

申请日：2016-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shou-Zen Chang ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Kai-Chiang Wu ,  Ming-Kai Liu

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/498 ,  H01L23/528 ,  H01L23/552 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/22 ,  H01L21/60

Abstract: An integrated fan-out package including an insulating encapsulation, a radio frequency integrated circuit (RF-IC), an antenna, a ground conductor, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The RF-IC, the antenna, and the ground conductor are embedded in the insulating encapsulation. The ground conductor is between the RF-IC and the antenna. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals, the antenna, and the ground conductor. A method of fabricating the integrated fan-out package is also provided.

公开(公告)号：US20180366347A1

公开(公告)日：2018-12-20

申请号：US15627457

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Nan-Chin Chuang ,  Ching-Feng Yang ,  Kai-Chiang Wu

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/762

CPC classification number: H01L21/561 ,  H01L21/762 ,  H01L21/76254 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20

Abstract: An integrated fan-out package having a multi-band antenna and a method of forming the same are disclosed. An integrated fan-out package includes a semiconductor die, a molding layer and a plurality of through integrated fan-out vias. The molding layer is aside the semiconductor die. The through integrated fan-out vias are through the molding layer and arranged to form a plurality of dipole antennas. At least one of the plurality of dipole antennas includes two dipole arms each having a transmitting strip and a radiating strip connected to the transmitting part, and the radiating strip has a first part, a second part and a filter part between and in contact with the first part and the second part. The cross-sectional area of the filter part is less than the cross-sectional area of the first part or the second part of the radiating strip.

公开(公告)号：US10157859B2

公开(公告)日：2018-12-18

申请号：US15867080

申请日：2018-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shou-Zen Chang ,  Chi-Ming Huang ,  Kai-Chiang Wu ,  Sen-Kuei Hsu ,  Hsin-Yu Pan ,  Han-Ping Pu ,  Albert Wan

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device. The semiconductor device structure includes a second conductive shielding layer under the first device. The first device is between the first conductive shielding layer and the second conductive shielding layer, and the second conductive shielding layer has a plurality of second openings.

公开(公告)号：US09875972B1

公开(公告)日：2018-01-23

申请号：US15210067

申请日：2016-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shou-Zen Chang ,  Chi-Ming Huang ,  Kai-Chiang Wu ,  Sen-Kuei Hsu ,  Hsin-Yu Pan ,  Han-Ping Pu ,  Albert Wan

IPC: H01L23/552 ,  H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/552 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/5382 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06537 ,  H01L2225/06555

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device.

公开(公告)号：US12266619B2

公开(公告)日：2025-04-01

申请号：US18358991

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kai-Chiang Wu ,  Chung-Shi Liu ,  Shou Zen Chang ,  Chao-Wen Shih

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L25/00 ,  H01L25/10 ,  H01P3/00 ,  H01Q1/22 ,  H01Q1/38 ,  H01Q9/04 ,  H01Q21/06

Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.

公开(公告)号：US20240297131A1

公开(公告)日：2024-09-05

申请号：US18663697

申请日：2024-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hao Tsai ,  Chia-Chia Lin ,  Kai-Chiang Wu ,  Chuei-Tang Wang ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/14 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/525 ,  H01L23/66 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L24/04 ,  H01L21/486 ,  H01L21/56 ,  H01L23/145 ,  H01L23/31 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/66 ,  H01L24/13 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/071 ,  H01L28/10 ,  H01L21/561 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/02205 ,  H01L2224/02215 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/10122 ,  H01L2224/13024 ,  H01L2224/18 ,  H01L2224/92244

Abstract: An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.