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    Floating body germanium phototransistor
    71.
    发明申请
    Floating body germanium phototransistor 有权
    浮体锗光电晶体管

    公开(公告)号：US20070001163A1

    公开(公告)日：2007-01-04

    申请号：US11174035

    申请日：2005-07-01

    申请人： Jong-Jan Lee ,  Sheng Hsu ,  Jer-Shen Maa ,  Douglas Tweet

    发明人： Jong-Jan Lee ,  Sheng Hsu ,  Jer-Shen Maa ,  Douglas Tweet

    IPC分类号： H01L31/00

    CPC分类号： H01L31/1136 ,  H01L31/028 ,  H01L31/1808 ,  Y02E10/547

    摘要： A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.

    摘要翻译： 提出了一种浮体锗（Ge）光电晶体管及其制造工艺。 该方法包括：提供硅（Si）衬底; 选择性地形成覆盖Si衬底的绝缘体层; 使用液相外延（LPE）工艺形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成覆盖所述沟道区的栅极电介质，栅电极和栅极间隔; 并且在Ge层中形成源/漏区。 LPE工艺包括用具有大于第一温度的熔化温度的材料包封Ge，并且使用低于第一温度的温度来熔化Ge。 LPE工艺包括：形成覆盖沉积Ge的介电层; 融化Ge; 并且响应于冷却Ge，将外延生长前沿从下面的Si衬底表面横向传播到Ge中。

    Method for forming an infrared photodetector with a vertical optical path
    72.
    发明申请
    Method for forming an infrared photodetector with a vertical optical path 审中-公开
    用于形成具有垂直光路的红外光电探测器的方法

    公开(公告)号：US20060189151A1

    公开(公告)日：2006-08-24

    申请号：US11384121

    申请日：2006-03-17

    申请人： Douglas Tweet ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Hsu

    发明人： Douglas Tweet ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Hsu

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L31/035281 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L31/101 ,  H01L31/1812 ,  Y02E10/50

    摘要： Provided are a SiGe vertical optical path and a method for selectively forming a SiGe optical path normal structure for IR photodetection. The method comprises: forming a Si substrate surface; forming a Si feature, normal with respect to the Si substrate surface, such as a trench, via, or pillar; and, selectively forming a SiGe optical path overlying the Si normal feature. In some aspects, the Si substrate surface is formed a first plane and the Si normal feature has walls (sidewalls), normal with respect to the Si substrate surface, and a surface in a second plane, parallel to the first plane. Then, selectively forming a SiGe optical path overlying the Si normal feature includes forming a SiGe vertical optical path overlying the normal feature walls.

    摘要翻译： 提供了SiGe垂直光路和用于选择性地形成用于IR光电检测的SiGe光路法线结构的方法。 该方法包括：形成Si衬底表面; 形成Si特征，相对于诸如沟槽，通孔或支柱的Si衬底表面是正常的; 并且选择性地形成覆盖Si正常特征的SiGe光路。 在一些方面，Si衬底表面形成第一平面，并且Si正常特征具有相对于Si衬底表面法线的壁（侧壁）和平行于第一平面的第二平面中的表面。 然后，选择性地形成覆盖Si正常特征的SiGe光路包括形成覆盖正常特征壁的SiGe垂直光路。

    Silicon phosphor electroluminescence device with nanotip electrode
    73.
    发明申请
    Silicon phosphor electroluminescence device with nanotip electrode 有权
    具有纳米尖电极的硅荧光体电致发光器件

    公开(公告)号：US20060180817A1

    公开(公告)日：2006-08-17

    申请号：US11061946

    申请日：2005-02-17

    申请人： Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

    发明人： Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

    IPC分类号： H01L27/15

    CPC分类号： H05B33/145

    摘要： An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.

    摘要翻译： 提供了一种电致发光（EL）器件和用于制造具有纳米尖端电极的所述器件的方法。 该方法包括：形成具有纳米尖端的底部电极; 在所述纳米尖端附近形成Si磷光体层; 并形成透明的顶部电极。 Si荧光体层介于底部和顶部电极之间。 纳米尖端可以具有约50纳米或更小的尖端基部尺寸，5至50nm范围内的尖端高度，以及每平方毫米大于100纳米尖端的纳米密度密度。 通常，纳米尖端由氧化铱（IrOx）纳米尖端形成。 MOCVD工艺形成Ir底部电极。 IrOx纳米尖嘴从Ir生长。 在一个方面，Si磷光体层是SRSO层。 响应于SRSO退火步骤，形成具有1至10nm范围内的尺寸的纳米晶体的纳米晶SRSO。

    Pt/PGO etching process for FeRAM applications
    75.
    发明申请
    Pt/PGO etching process for FeRAM applications 失效

    公开(公告)号：US20060040413A1

    公开(公告)日：2006-02-23

    申请号：US10923381

    申请日：2004-08-20

    申请人： Fengyan Zhang ,  Bruce Ulrich ,  Lisa Stecker ,  Sheng Hsu

    发明人： Fengyan Zhang ,  Bruce Ulrich ,  Lisa Stecker ,  Sheng Hsu

    IPC分类号： H01L21/00

    CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L27/1085 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

    摘要： A method of etching a noble metal top electrode on a ferroelectric layer while preserving the ferroelectric properties of the ferroelectric layer and removing etching residue includes preparing a substrate; depositing a barrier layer on the substrate; depositing a bottom electrode layer on the barrier layer; depositing a ferroelectric layer on the bottom electrode layer; depositing a noble metal top electrode layer on the ferroelectric layer; depositing an adhesion layer on the top electrode layer; depositing a hard mask layer on the adhesion layer; patterning the hard mask; etching the noble metal top electrode layer in an initial etching step at a predetermined RF bias power, which produces etching residue; and over etching the noble metal top electrode layer and ferroelectric layer at an RF bias power lower than that of the predetermined RF bias power to remove etching residue from the initial etching step.

    Asymmetric-area memory cell
    77.
    发明申请
    Asymmetric-area memory cell 有权
    非对称区记忆单元

    公开(公告)号：US20050124112A1

    公开(公告)日：2005-06-09

    申请号：US10730726

    申请日：2003-12-08

    申请人： Sheng Hsu ,  Fengyan Zhang

    发明人： Sheng Hsu ,  Fengyan Zhang

    IPC分类号： H01L21/28 ,  G11C11/15 ,  G11C13/00 ,  H01L21/3205 ,  H01L21/8239 ,  H01L21/8246 ,  H01L23/52 ,  H01L27/105 ,  H01L27/115 ,  H01L27/22 ,  H01L27/24 ,  H01L29/68 ,  H01L43/08 ,  H01L45/00 ,  H01L21/8242

    CPC分类号： H01L27/105 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/52 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

    摘要： An asymmetric-area memory cell, and a fabrication method for forming an asymmetric-area memory cell, are provided. The method comprises: forming a bottom electrode having an area; forming a CMR memory film overlying the bottom electrode, having an asymmetric area; and, forming a top electrode having an area, less than the bottom electrode area, overlying the CMR film. In one aspect, the CMR film has a first area adjacent the top electrode and a second area, greater than the first area, adjacent the bottom electrode. Typically, the CMR film first area is approximately equal to the top electrode area, although the CMR film second area may be less than the bottom electrode area.

    摘要翻译： 提供了一种不对称区域存储单元和用于形成非对称区域存储单元的制造方法。 该方法包括：形成具有面积的底部电极; 形成覆盖在底部电极上的具有不对称区域的CMR存储膜; 并且形成覆盖CMR膜的具有小于底部电极区域的面积的顶部电极。 在一个方面，CMR膜具有邻近顶部电极的第一区域和与底部电极相邻的大于第一区域的第二区域。 通常，尽管CMR膜的第二区域可能小于底部电极区域，但是CMR膜的第一区域大致等于顶部电极区域。

    Sacrificial shallow trench isolation oxide liner for strained-silicon channel CMOS devices
    78.
    发明申请
    Sacrificial shallow trench isolation oxide liner for strained-silicon channel CMOS devices 有权
    用于应变硅沟道CMOS器件的牺牲浅沟槽隔离氧化层

    公开(公告)号：US20050101077A1

    公开(公告)日：2005-05-12

    申请号：US10985462

    申请日：2004-11-09

    申请人： Jong-Jan Lee ,  Sheng Hsu

    发明人： Jong-Jan Lee ,  Sheng Hsu

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L21/336

    CPC分类号： H01L21/823878 ,  H01L21/76224 ,  H01L21/823807

    摘要： A strained-silicon (Si) channel CMOS device shallow trench isolation (STI) oxide region, and method for forming same have been provided. The method comprises: forming a Si substrate; forming a relaxed-SiGe layer overlying the Si substrate, or a SiGe on insulator (SGOI) substrate with a buried oxide (BOX) layer; forming a strained-Si layer overlying the relaxed-SiGe layer; forming a silicon oxide layer overlying the strained-Si layer; forming a silicon nitride layer overlying the silicon oxide layer; etching the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface; forming a sacrificial oxide liner on the STI trench surface; in response to forming the sacrificial oxide liner, rounding and reducing stress at the STI trench corners; removing the sacrificial oxide liner; and, filling the STI trench with silicon oxide.

    摘要翻译： 已经提供了应变硅（Si）沟道CMOS器件浅沟槽隔离（STI）氧化物区域及其形成方法。 该方法包括：形成Si衬底; 形成覆盖在Si衬底上的弛豫SiGe层或者具有掩埋氧化物（BOX）层的绝缘体上硅锗（SGOI）衬底; 形成覆盖弛豫SiGe层的应变Si层; 形成覆盖在应变Si层上的氧化硅层; 形成覆盖所述氧化硅层的氮化硅层; 蚀刻氮化硅层，氧化硅层，应变Si层和弛豫SiGe层，形成具有沟槽角和沟槽表面的STI沟槽; 在STI沟槽表面上形成牺牲氧化物衬垫; 响应于形成牺牲氧化物衬垫，在STI沟槽角处减少应力; 去除牺牲氧化物衬垫; 并用氧化硅填充STI沟槽。

    Cross-point resistor memory array
    79.
    发明申请
    Cross-point resistor memory array 有权
    交叉点电阻存储器阵列

    公开(公告)号：US20050083757A1

    公开(公告)日：2005-04-21

    申请号：US10971204

    申请日：2004-10-21

    申请人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

    发明人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

    IPC分类号： G11C11/15 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24 ,  G11C7/00

    CPC分类号： G11C11/15 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/72 ,  H01L27/24

    摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

    摘要翻译： 提供了电阻式交叉点存储器件，以及制造和使用方法。 存储器件由介于上电极和下电极之间的电阻存储器材料的有源层组成。 在上电极和下电极的交叉点处位于电阻性存储器材料内的位区域具有响应于施加一个或更多个电压脉冲而能够在一定范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。 在电阻性存储器材料和下电极之间的界面处形成二极管，其可以形成为掺杂区域。 电阻交叉点存储器件通过在衬底内掺杂一行极性形成，然后将相反极性的线的掺杂区域形成二极管。 然后在二极管上形成一层电阻记忆材料覆盖底部电极的底部电极。 然后可以以倾斜的角度添加顶部电极以形成由线和顶部电极限定的交叉点阵列。