公开(公告)号：US20160049946A1

公开(公告)日：2016-02-18

申请号：US14461098

申请日：2014-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Chun LIAO

IPC: H03L7/081 ,  G04F10/00

CPC classification number: H03L7/0991 ,  G04F10/005 ,  H03L7/0812 ,  H03L7/085 ,  H03L2207/50

Abstract: An all digital phase locked loop comprises a time-to-digital converter and a configurable multiplier. The time-to-digital converter is configured to output a digital code based on a phase difference between a reference clock signal and a variable clock signal. The configurable multiplier is coupled with the time-to-digital converter. The configurable multiplier has a selectable bit size. The selectable bit size is based on a defined minimum number of bits to obtain a reciprocal of a variable clock period. The minimum number of bits is based on a comparison of a first number of bits of a divisor with a second number of bits of a quotient. The time-to-digital converter is configured to multiply the digital code by the reciprocal of the variable clock period to output a fractional error correction value.

Abstract translation: 全数字锁相环包括时间 - 数字转换器和可配置乘法器。 该时间 - 数字转换器被配置为基于参考时钟信号和可变时钟信号之间的相位差来输出数字码。 可配置的乘法器与时间 - 数字转换器耦合。 可配置的乘法器具有可选择的位大小。 可选择的比特大小基于所定义的最小比特数来获得可变时钟周期的倒数。 最小比特数是基于除数的第一比特数与商的第二比特数的比较。 时间数字转换器被配置为将数字代码乘以可变时钟周期的倒数以输出分数误差校正值。

公开(公告)号：US09250612B2

公开(公告)日：2016-02-02

申请号：US14218637

申请日：2014-03-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mao-Hsuan Chou ,  Jinn-Yeh Chien

IPC: H03M1/50 ,  G04F10/00

CPC classification number: G04F10/005

Abstract: An embodiment is a device including a control circuit, a time-to-digital converter circuit coupled having a first output coupled to a first input of the control circuit, and a gating circuit having a first input coupled to a first signal, a second input coupled to a second signal, and an output coupled to a first input of the time-to-digital converter circuit, an output of the control circuit coupled to a second input of the time-to-digital converter circuit and to a third input of the gating circuit.

Abstract translation: 一个实施例是一种装置，其包括控制电路，耦合到具有耦合到控制电路的第一输入端的第一输出的时 - 数转换器电路和具有耦合到第一信号的第一输入的门控电路，第二输入 耦合到第二信号，以及耦合到所述时间 - 数字转换器电路的第一输入的输出，所述控制电路的输出耦合到所述时间 - 数字转换器电路的第二输入端，并输出到所述时间数字转换器电路的第三输入端 门电路。

公开(公告)号：US20160028411A1

公开(公告)日：2016-01-28

申请号：US14339459

申请日：2014-07-24

Applicant: MEDIATEK INC.

Inventor： Chun-Ming Kuo ,  Chii-Horng Chen ,  Shih-Chi Shen ,  Ai-Hsuan Liu

IPC: H03L7/16 ,  H03L7/099 ,  G04F10/00

CPC classification number: H03L7/16 ,  G04F10/005 ,  H03L7/099 ,  H03L7/1075 ,  H03L2207/50

Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.

Abstract translation: 频率合成器包括锁相环（PLL）和环路带宽控制器。 PLL根据参考时钟产生输出时钟。 环路带宽控制器检查至少一个指示PLL的注入拉/推的指示器，以配置PLL的环路带宽。 在一个示例性设计中，环路带宽控制器通过控制PLL中包括的环路滤波器的配置来设置PLL的环路带宽。 例如，PLL是全数字锁相环（ADPLL），环路滤波器是ADPLL的数字环路滤波器。

公开(公告)号：US09231602B1

公开(公告)日：2016-01-05

申请号：US14490115

申请日：2014-09-18

Applicant: Intel IP Corporation

Inventor： Elan Banin ,  Rotem Banin ,  Ofir Degani ,  Ran Shimon ,  Ashoke Ravi

IPC: H03L7/06 ,  H03L7/08 ,  G04F10/00

CPC classification number: G04F10/005 ,  H03L7/085 ,  H03L2207/50

Abstract: A digital phase locked loop operates with a time-to-digital converter and an a-priori-probability-phase-estimation component or estimator component that estimates the un-quantized phase associated with a quantization output of the time-to-digital converter. The time-to-digital converter generates a quantized value as the quantization output from a local oscillator signal of a local oscillator and a reference signal of a reference clock. The estimation component estimates a phase value from the quantized values as a function of a-priori data related to the time-to-digital converter and boundaries of the quantized value.

Abstract translation: 数字锁相环用时间数字转换器和估计与时间数字转换器的量化输出相关联的未量化相位的先验概率相位估计分量或估计器分量进行操作。 时间 - 数字转换器产生量化值作为本地振荡器的本地振荡器信号和参考时钟的参考信号的量化输出。 估计分量从作为与时间 - 数字转换器相关的先验数据和量化值的边界的函数的量化值估计相位值。

公开(公告)号：US20150268633A1

公开(公告)日：2015-09-24

申请号：US14218637

申请日：2014-03-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mao-Hsuan Chou ,  Jinn-Yeh Chien

IPC: G04F10/00

CPC classification number: G04F10/005

Abstract: According to various embodiments described herein, a device includes a control circuit, a time-to-digital converter circuit coupled having a first output coupled to a first input of the control circuit, and a gating circuit having a first input coupled to a first signal, a second input coupled to a second signal, and an output coupled to a first input of the time-to-digital converter circuit, an output of the control circuit coupled to a second input of the time-to-digital converter circuit and to a third input of the gating circuit.

Abstract translation: 根据本文描述的各种实施例，一种设备包括控制电路，时间 - 数字转换器电路，其耦合具有耦合到控制电路的第一输入的第一输出，以及门控电路，其具有耦合到第一信号的第一输入 ，耦合到第二信号的第二输入和耦合到所述时间 - 数字转换器电路的第一输入的输出，所述控制电路的输出耦合到所述时间 - 数字转换器电路的第二输入端，以及 门控电路的第三输入。

公开(公告)号：US20150256186A1

公开(公告)日：2015-09-10

申请号：US14626202

申请日：2015-02-19

Applicant: Sony Corporation

Inventor： Takeshi Matsubara ,  Masahisa Tamura

IPC: H03L7/08 ,  G04F10/00 ,  G05F3/02

CPC classification number: H03L7/08 ,  G04F10/005

Abstract: An electronic circuit includes a plurality of delay elements configured to delay a clock signal by a delay time and to supply the delayed clock signal as a delay signal, the delay time being shorter with a higher power source voltage; a delay time acquisition unit configured to acquire the delay time based on a value of the delay signal; and a voltage controller configured to perform a voltage control process in which the power source voltage is controlled to be high in a case where the acquired delay time is longer than a predetermined desired value and the power source voltage is controlled to be low in a case where the acquired delay time is shorter than the predetermined desired value.

Abstract translation: 电子电路包括多个延迟元件，其被配置为将时钟信号延迟延迟时间，并将延迟时钟信号提供为延迟信号，延迟时间随着较高的电源电压而变短; 延迟时间获取单元，被配置为基于所述延迟信号的值来获取所述延迟时间; 以及电压控制器，被配置为执行电压控制处理，其中在所获取的延迟时间长于预定期望值的情况下，将电源电压控制为高，并且电源电压被控制为低的情况 其中获取的延迟时间短于预定的期望值。

公开(公告)号：US20150248114A1

公开(公告)日：2015-09-03

申请号：US14714000

申请日：2015-05-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jinn-Yeh Chien

IPC: G04F10/00

CPC classification number: G04F10/005 ,  H03K5/133

Abstract: A device includes a delay line, a first readout circuit electrically connected to the delay line, a second readout circuit electrically connected to the delay line, and a phase interpolator electrically connected to the second readout circuit.

Abstract translation: 一种装置包括延迟线，电连接到延迟线的第一读出电路，电连接到延迟线的第二读出电路，以及电连接到第二读出电路的相位插值器。

公开(公告)号：US09116511B2

公开(公告)日：2015-08-25

申请号：US13278879

申请日：2011-10-21

Applicant: Seung-Cheol Bang ,  Hyung Chul Lim ,  Jong Uk Park

Inventor： Seung-Cheol Bang ,  Hyung Chul Lim ,  Jong Uk Park

IPC: G04F10/00 ,  G04G3/04 ,  G04F10/04

CPC classification number: G04F10/005 ,  G04F10/00 ,  G04F10/04 ,  G04G3/04

Abstract: The present invention makes it possible to measure a precision event time in such a way to make a reference data in accordance with a standard time reference frequency signal and to make a measurement data by using an apparatus with the same structure as a reference data with respect to a signal to be measured and to compare the measurement data with a reference data, whereby temperature effects can be minimized by making the time changes due to temperature changes occurring between two apparatuses happen equally, by providing the same structure and parts to a reference signal circuit apparatus for an event time measurement and a signal circuit apparatus to be measured, and the zero point adjustment is performed during the real time operation, so the system is not needed to stop.

Abstract translation: 本发明使得可以以这样的方式测量精确事件时间，以便根据标准时间参考频率信号作出参考数据，并且通过使用具有与参考数据相同结构的装置来制作测量数据， 与要测量的信号相比较，并将测量数据与参考数据进行比较，从而通过使两个装置之间发生的温度变化引起的时间变化可以使温度效应最小化，通过将相同的结构和部件提供给参考信号 用于事件时间测量的电路装置和待测量的信号电路装置，并且在实时操作期间执行零点调整，因此系统不需要停止。

公开(公告)号：US20150212494A1

公开(公告)日：2015-07-30

申请号：US14681206

申请日：2015-04-08

Applicant: IQ-Analog Corporation

Inventor： Mikko Waltari

IPC: G04F10/00 ,  H03M1/12

CPC classification number: G04F10/005 ,  H03M1/1295 ,  H03M1/50 ,  H03M1/502 ,  H03M1/60

Abstract: A Traveling Pulse Wave Quantization method is provided for converting a time sensitive signal to a digital value. A first stop signal is delayed by a first time delay, a first plurality of times, to create a delayed first stop signal. A clock signal is delayed by a second time delay, a first plurality of times, to create a delayed clock signal first period. Each second time delay is associated with a corresponding first time delay, and the second time delay is greater than the first time delay. When the delayed first stop signal occurs before the delayed clock signal first period, a count of the delays is stopped and converted into a digital or thermometer value. An accurate resampled value is provided regardless of the duration in delay between the first stop signal and a second stop signal that is accepted after the first stop signal.

Abstract translation: 提供了一种将时间敏感信号转换为数字值的行波脉冲波量化方法。 第一停止信号被延迟第一时间延迟，第一次多次，以产生延迟的第一停止信号。 时钟信号被延迟第二时间延迟，第一次多次，以产生延迟的时钟信号第一周期。 每个第二时间延迟与对应的第一时间延迟相关联，并且第二时间延迟大于第一时间延迟。 当延迟的第一停止信号在延迟时钟信号第一周期之前发生时，延迟的计数被停止并转换成数字或温度计值。 无论第一停止信号和第一停止信号之后接受的第二停止信号的延迟持续时间如何，均提供精确的重采样值。

公开(公告)号：US20150205267A1

公开(公告)日：2015-07-23

申请号：US14161714

申请日：2014-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsieh-Hung Hsieh ,  Yen-Jen Chen ,  Chewn-Pu Jou

IPC: G04F10/00 ,  H03K5/159 ,  H03L7/085

CPC classification number: G04F10/005 ,  G04F10/105 ,  H03K5/159 ,  H03L7/085 ,  H03M1/50

Abstract: A time-to-digital converter (TDC) comprises a first delay line including a plurality of first delay cells connected in series, wherein each of the first delay cells include a plurality of first delay units connected in series, wherein each of the first delay units includes a tunable PMOS transistor, a first poly on oxide definition (OD) edge (PODE) transistor, and a pull-up PMOS transistor. The TDC further comprises a second delay line including a plurality of second delay cells connected in series, wherein each of the second delay cells include a plurality of second delay units connected in series, wherein each of the second delay units includes a tunable NMOS transistor, a second PODE transistor, and a pull-down NMOS transistor.

Abstract translation: 时间数字转换器（TDC）包括包括串联连接的多个第一延迟单元的第一延迟线，其中每个第一延迟单元包括串联连接的多个第一延迟单元，其中第一延迟 单元包括可调谐PMOS晶体管，第一多晶氧化物界定（OD）边缘（PODE）晶体管和上拉PMOS晶体管。 TDC还包括包括串联连接的多个第二延迟单元的第二延迟线，其中每个第二延迟单元包括串联连接的多个第二延迟单元，其中每个第二延迟单元包括可调NMOS晶体管， 第二PODE晶体管和下拉式NMOS晶体管。