公开(公告)号：US20160276001A1

公开(公告)日：2016-09-22

申请号：US15018180

申请日：2016-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeunghwan Park ,  Sunghoon KIM

IPC: G11C7/10 ,  G11C7/18

CPC classification number: G11C7/18 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/106 ,  G11C16/26 ,  H01L27/0207 ,  H01L27/11573 ,  H01L27/11582

Abstract: The inventive concepts relate to nonvolatile memory devices. The nonvolatile memory devices may include a memory cell array, and a page buffer circuit connected to the memory cell array through bit lines. The page buffer circuit may comprise a substrate, bit line selection transistors on the substrate and connected to respective ones of the bit lines, and latches on the substrate connected to the bit line selection transistors through lines. The lines may be on a first plane above and parallel to a top surface of the substrate, and may be connected to respective ones of the bit line selection transistors through first contacts. The bit lines may be on a second plane above and parallel to a top surface of the substrate, and may be connected to respective ones of the bit line selection transistors through second contacts.

Abstract translation: 本发明构思涉及非易失性存储器件。 非易失性存储器件可以包括存储单元阵列和通过位线连接到存储单元阵列的页缓冲器电路。 页面缓冲电路可以包括衬底，衬底上的位线选择晶体管，并且连接到相应的位线，以及通过线连接到位线选择晶体管的衬底上的锁存器。 线可以在衬底的顶表面上方并平行的第一平面上，并且可以通过第一接触连接到位线选择晶体管中的相应位置。 位线可以在衬底的上表面上方并且平行于第二平面，并且可以通过第二触点连接到相应的位线选择晶体管。

公开(公告)号：US20160240232A1

公开(公告)日：2016-08-18

申请号：US15138998

申请日：2016-04-26

Applicant: SK hynix Inc.

Inventor： Dong Hwan LEE

IPC: G11C7/10

CPC classification number: G11C29/44 ,  G11C7/18 ,  G11C16/0483 ,  G11C16/3454 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10885

Abstract: A semiconductor device includes a semiconductor device, comprising a memory cell array including a plurality of memory cells connected to a first bit line and a second bit line, respectively, a page buffer group, and bit line selection circuits including a plurality of selection circuit blocks to connect the first bit lines or the second bit lines to the page buffer group, wherein each of the selection circuit blocks includes a first contact region and a second contact region to which the first and second bit lines coupled, and same bit lines of the first and second bit lines are coupled to contact regions adjacent to one another of the first and second contact regions included in bit line selection circuits adjacent to one another of the bit line selection circuits.

Abstract translation: 半导体器件包括半导体器件，包括分别包括连接到第一位线和第二位线的多个存储器单元的存储单元阵列，页面缓冲器组以及包括多个选择电路块的位线选择电路 将第一位线或第二位线连接到页缓冲器组，其中每个选择电路块包括第一接触区域和耦合第一和第二位线的第二接触区域，以及第 第一和第二位线被耦合到包括在位线选择电路中彼此相邻的位线选择电路中的第一和第二接触区域彼此相邻的接触区域。

公开(公告)号：US09419007B2

公开(公告)日：2016-08-16

申请号：US14570766

申请日：2014-12-15

Applicant: SK hynix Inc.

Inventor： Jae Kwan Kwon

IPC: H01L27/11 ,  G11C16/08 ,  G11C16/04 ,  H01L27/115 ,  G11C7/18

CPC classification number: H01L27/11556 ,  G11C7/18 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device includes a first vertical memory string connected to a common source line, a second vertical memory string connected to a bit line, a pipe transistor suitable for selectively connecting the first and second vertical memory strings based on a block selection signal, and a plurality of transistors suitable for selectively connecting local lines of the first and second vertical memory strings to corresponding global lines based on the block selection signal.

Abstract translation: 半导体器件包括连接到公共源极线的第一垂直存储器串，连接到位线的第二垂直存储器串，适于基于块选择信号有选择地连接第一和第二垂直存储器串的管晶体管，以及 多个晶体管适于基于块选择信号选择性地将第一和第二垂直存储器串的本地线连接到对应的全局线。

公开(公告)号：US09412439B1

公开(公告)日：2016-08-09

申请号：US14599327

申请日：2015-01-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. ,  National Chiao Tung University

Inventor： Ming-Long Fan ,  Pi-Ho Hu ,  Yin-Nien Chen ,  Pin Su ,  Ching-Te (Kent) Chuang ,  Samuel C. Pan

IPC: G11C11/41 ,  G11C11/419 ,  G11C11/412 ,  G11C11/417

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C7/18 ,  G11C11/412 ,  G11C11/417

Abstract: A circuit includes a hybrid switch, which includes a Tunnel Field-Effect Transistor (TFET) having a first source, a first drain, and a first gate. The hybrid switch further includes a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) connected to the TFET in parallel, with the MOSFET including a second source connected to the first source, a second drain connected to the first drain, and a second gate connected to the first gate.

Abstract translation: 电路包括混合开关，其包括具有第一源极，第一漏极和第一栅极的隧道场效应晶体管（TFET）。 混合开关还包括并联连接到TFET的金属氧化物半导体场效应晶体管（MOSFET），其中MOSFET包括连接到第一源的第二源极，连接到第一漏极的第二漏极和第二漏极 门连接到第一个门。

公开(公告)号：US20160210192A1

公开(公告)日：2016-07-21

申请号：US15083122

申请日：2016-03-28

Applicant: INTEL CORPORATION

Inventor： Jaydeep P. Kulkarni ,  Keith A. Bowman ,  James W. Tschanz ,  Vivek K. De

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F9/30141 ,  G06F9/3861 ,  G06F11/0751 ,  G06F11/1008 ,  G11C7/18 ,  G11C29/42 ,  G11C29/52

Abstract: The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.

Abstract translation: 所公开的系统和方法检测并校正由于减少或消除CPU的电源电压保护带和​​/或频率保护带而可能发生的寄存器文件读取路径错误，从而提高了系统的总体能量效率。

公开(公告)号：US09361973B2

公开(公告)日：2016-06-07

申请号：US14228899

申请日：2014-03-28

Applicant: Cypress Semiconductor Corporation

Inventor： Dinesh Maheshwari

IPC: G11C7/18 ,  G11C11/413 ,  G11C7/10 ,  G11C11/419 ,  G11C5/02 ,  G11C8/12

CPC classification number: G11C11/413 ,  G11C5/025 ,  G11C7/1075 ,  G11C7/18 ,  G11C8/12 ,  G11C11/419 ,  G11C2207/2209

Abstract: An integrated circuit (IC) can include M memory banks, where M is greater than 2, and each memory bank is separately accessible according to a received address value; N channels, where N is greater than 2, and each channel includes its own a data connections, address connections, and control input connections for executing a read or write access to one of the memory banks in synchronism with a clock signal; and a controller subsystem configured to control accesses between the channels and the memory banks, including up to an access on every channel on consecutive cycles of the clock signal.

Abstract translation: 集成电路（IC）可以包括M个存储体，其中M大于2，并且每个存储体可根据接收到的地址值分开存取; N个通道，其中N大于2，并且每个通道包括其自己的数据连接，地址连接和控制输入连接，用于与时钟信号同步地执行对存储体之一的读或写访问; 以及控制器子系统，被配置为控制所述通道和所述存储体之间的访问，包括在所述时钟信号的连续周期上的每个通道上的访问。

公开(公告)号：US09355718B2

公开(公告)日：2016-05-31

申请号：US14689409

申请日：2015-04-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Everardo Torres Flores ,  Hernan A. Castro ,  Jeremy M. Hirst

IPC: G11C7/00 ,  G11C13/00 ,  H01L23/522 ,  G11C5/02 ,  G11C5/06 ,  H01L27/02 ,  G11C7/18 ,  H01L27/24

CPC classification number: G11C13/0021 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  G11C13/0004 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/2427 ,  H01L27/2481 ,  H01L2924/00 ,  H01L2924/0002

Abstract: For multi-level interconnect metallization, each metal level maintains a parallel line arrangement within a region, and the lines of each adjacent metal level are orthogonal or otherwise cross with one another. Vertical shunting among levels for routing in different directions employs short paddles that stay within the parallel scheme, and multiple paddles within a region at the same metal level can be co-linear. Parallel lines in the same metal level can be rotated with respect to one another in adjacent regions, for example to better interface with driver circuitry with orthogonal orientations in the different regions.

公开(公告)号：US09355711B2

公开(公告)日：2016-05-31

申请号：US14624094

申请日：2015-02-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Bing Wang

IPC: G11C7/00 ,  G11C11/419 ,  G11C7/10 ,  G11C7/18 ,  G11C5/02 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/18 ,  G11C11/418 ,  G11C2207/2227

Abstract: A circuit includes a first data line, a first plurality of memory cells coupled with the first data line, and a data transfer circuit coupled with the first data line. The data transfer circuit includes an output logic gate. The data transfer circuit is configured to, in a first operation mode in which the first plurality of memory cells is in a standby mode, set an output node of the output logic gate to be free from electrically coupled with a reference voltage and a supply voltage through the output logic gate. The data transfer circuit is configured to, in a second operation mode in which a memory cell of the first plurality of memory cells is selected to be read, set the output node of the output logic gate to be either electrically coupled with the reference voltage or with the supply voltage through the output logic gate.

Abstract translation: 电路包括第一数据线，与第一数据线耦合的第一多个存储单元，以及与第一数据线耦合的数据传输电路。 数据传输电路包括输出逻辑门。 数据传送电路被配置为在第一多个存储单元处于待机模式的第一操作模式中，将输出逻辑门的输出节点设置为与参考电压和电源电压电耦合 通过输出逻辑门。 数据传输电路被配置为在其中选择要读取第一多个存储单元的存储单元的第二操作模式中，将输出逻辑门的输出节点与参考电压电耦合，或 电源电压通过输出逻辑门。

公开(公告)号：US09349452B2

公开(公告)日：2016-05-24

申请号：US13788183

申请日：2013-03-07

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Mohan V. Dunga ,  Masaaki Higashitani

IPC: G11C16/04 ,  H01L29/66 ,  H01L29/788 ,  G11C7/18 ,  G11C16/24 ,  H01L27/115

CPC classification number: G11C16/0425 ,  G11C7/18 ,  G11C16/0483 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/788

Abstract: A non-volatile storage system includes a plurality of groups of connected non-volatile storage elements. Each group comprises multiple connected data non-volatile storage elements and multiple select gates on a common side of the data non-volatile storage elements. The multiple select gates comprise a first select gate and a second select gate. The first select gate has a first threshold voltage for a first subset of the groups and a second threshold voltage for a second subset of the groups due to active area implantation for the second subset of groups that causes the second threshold voltage to be lower than the first threshold voltage. The second select gate of each group has a programmable threshold voltage. Each of the plurality of bit lines are connected to multiple groups of connected non-volatile storage elements.

Abstract translation: 非易失性存储系统包括多组连接的非易失性存储元件。 每个组包括数据非易失性存储元件的公共侧上的多个连接的数据非易失性存储元件和多个选择栅极。 多个选择栅极包括第一选择栅极和第二选择栅极。 第一选择栅极具有用于组的第一子集的第一阈值电压和由于第二子集的有源区域注入导致第二阈值电压低于第二阈值电压的第二子集的第二阈值电压。 第一阈值电压。 每组的第二选择栅极具有可编程阈值电压。 多个位线中的每一个连接到多组连接的非易失性存储元件。

公开(公告)号：US09349439B2

公开(公告)日：2016-05-24

申请号：US14715636

申请日：2015-05-19

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki Yamamoto

IPC: G11C5/02 ,  G11C11/419 ,  G11C7/18 ,  G11C5/04 ,  G11C5/06 ,  G11C11/4097

CPC classification number: G11C11/419 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/413 ,  G11C2207/2227 ,  H01L21/84 ,  H01L27/1108 ,  H01L27/1203

Abstract: An intermediate mode is set between the active mode in which a threshold voltage is low and a standby mode in which a threshold voltage is high. When a mode is shifted from the active mode to the standby mode, the threshold voltage for the active mode is raised temporarily to a threshold voltage for the intermediate mode and then the threshold voltage for the intermediate mode is raised to the threshold voltage for the standby mode. When a mode is shifted from the standby mode to the active mode, the threshold voltage for the standby mode is lowered temporarily to the threshold voltage for the intermediate mode and then the threshold voltage for the intermediate mode is lowered to the threshold voltage for the active mode.

Abstract translation: 在阈值电压低的活动模式和阈值电压高的待机模式之间设定中间模式。 当模式从活动模式切换到待机模式时，主动模式的阈值电压暂时升高到中间模式的阈值电压，然后中间模式的阈值电压升高到待机模式的阈值电压 模式。 当模式从待机模式转换到活动模式时，待机模式的阈值电压临时降低到中间模式的阈值电压，然后中间模式的阈值电压降低到活动的阈值电压 模式。