公开(公告)号：US06861678B2

公开(公告)日：2005-03-01

申请号：US10623230

申请日：2003-07-18

申请人： Gregory E. Howard ,  Leland S. Swanson

发明人： Gregory E. Howard ,  Leland S. Swanson

IPC分类号： H01L21/337 ,  H01L29/808 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/66909 ,  H01L29/8083

摘要： We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a body region above the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

公开(公告)号：US06858885B2

公开(公告)日：2005-02-22

申请号：US10400410

申请日：2003-03-28

申请人： Atsushi Ebara

发明人： Atsushi Ebara

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/092 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L27/0266 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： A protection circuit for use in a semiconductor apparatus includes a first conductivity type semiconductor substrate, a second conductivity type first diffusion region formed on the semiconductor substrate, and a second conductivity type second diffusion region formed on the semiconductor substrate. The second diffusion region is distanced at a prescribed interval from the first diffusion region. The first diffusion region is electrically connected to a pad for electrically connecting the semiconductor apparatus to an outside region. The second diffusion region is electrically connected to a power supply voltage. At least a portion of each of the first and second diffusion regions is entirely formed right under a pad area having the pad.

摘要翻译： 用于半导体装置的保护电路包括第一导电型半导体衬底，形成在半导体衬底上的第二导电类型的第一扩散区和形成在半导体衬底上的第二导电类型的第二扩散区。 第二扩散区域与第一扩散区域以规定的间隔间隔开。 第一扩散区域电连接到用于将半导体器件电连接到外部区域的焊盘。 第二扩散区域电连接到电源电压。 第一扩散区域和第二扩散区域中的每一个的至少一部分完全形成在具有该焊盘的焊盘区域正下方。

公开(公告)号：US20050023565A1

公开(公告)日：2005-02-03

申请号：US10900720

申请日：2004-07-27

申请人： Steven Towle ,  Anna George

发明人： Steven Towle ,  Anna George

IPC分类号： H01L21/312 ,  H01L21/46 ,  H01L21/78 ,  H01L23/544 ,  H01L27/10 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L21/78 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/3124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/00014

摘要： In one embodiment there is provided a method comprising performing a sawing operation on a wafer; and treating the wafer to at least reduce a propagation of micro-cracks formed in the wafer during the sawing. In another embodiment there is provided a semi-conductor die comprising a substrate having a central first portion, and a peripheral second portion around the central first portion; an integrated circuit formed on the central first portion; and a guard ring disposed between the first and second portions of the substrate to prevent a propagation of cracks found in that second portion to the first portion, wherein the second portion includes micro-cracks filled with a crack-healing material to arrest propagation of the micro-cracks beyond the guard ring and into the central first portion.

摘要翻译： 在一个实施例中，提供了一种方法，包括在晶片上执行锯切操作; 并且在锯切期间处理晶片至少减少在晶片中形成的微裂纹的传播。 在另一个实施例中，提供了一种半导体管芯，其包括具有中心第一部分的基底和围绕中心第一部分的周边第二部分; 形成在所述中央第一部分上的集成电路; 以及保护环，其设置在所述基板的所述第一和第二部分之间，以防止在所述第二部分中发现的裂纹扩展到所述第一部分，其中所述第二部分包括填充有裂纹修复材料的微裂纹以阻止所述第二部分的传播 微裂纹超过保护环并进入中心第一部分。

公开(公告)号：US06841806B1

公开(公告)日：2005-01-11

申请号：US10602218

申请日：2003-06-24

申请人： Geoff W. Taylor ,  Jianhong Cai

发明人： Geoff W. Taylor ,  Jianhong Cai

IPC分类号： H01L27/08 ,  H01L29/15 ,  H01L29/74 ,  H01L31/111 ,  H01L31/0328

CPC分类号： H01L29/74 ,  H01L27/0817 ,  H01L29/155 ,  H01L31/1113

摘要： An integrated circuit includes a heterojunction thyristor device having an anode terminal, a cathode terminal, a first injector terminal operably coupled to a first quantum well channel disposed between the anode terminal and the cathode terminal, and a second injector terminal operably coupled to a second quantum well channel disposed between the anode terminal and the cathode terminal. Bias elements operate the heterojunction thyristor device in a mode that provides substantially linear voltage gain for electrical signals supplied to at least one of the first and second injector terminals for output to at least one output node. Preferably, the bias elements include a first DC current source operably coupled to an n-type modulation doped quantum well structure, a second DC current source operably coupled to a p-type modulation doped quantum well structure, a first bias resistance operably coupled between a high voltage supply and the anode terminal, and a second bias resistance operably coupled between the cathode terminal and a low voltage supply. The bias elements provide a current passing from the anode terminal to the cathode terminal that is below a characteristic hold current for the heterojunction thyristor device to thereby inhibit switching of the heterojunction thyristor device. The DC current provided by the DC current sources controls the amount of voltage gain provided by the heterojunction thyristor device.

摘要翻译： 集成电路包括具有阳极端子，阴极端子，可操作地耦合到设置在阳极端子和阴极端子之间的第一量子阱沟道的第一注入端子的异质结晶闸管器件和可操作地耦合到第二量子阱的第二注入器端子 阱通道设置在阳极端子和阴极端子之间。 偏置元件以对提供给第一和第二注入器端子中的至少一个的电信号提供基本上线性的电压增益以输出到至少一个输出节点的模式来操作异质结晶闸管器件。 优选地，偏置元件包括可操作地耦合到n型调制掺杂量子阱结构的第一DC电流源，可操作地耦合到p型调制掺杂量子阱结构的第二DC电流源，可操作地耦合在 高电压电源和阳极端子，以及可操作地耦合在阴极端子和低电压电源之间的第二偏置电阻。 偏置元件提供从阳极端子到阴极端子的电流，该电流低于异质结晶闸管器件的特性保持电流，从而阻止异质结晶闸管器件的切换。 由直流电流源提供的直流电流控制由异质结晶闸管器件提供的电压增益的量。

公开(公告)号：US6144046A

公开(公告)日：2000-11-07

申请号：US902332

申请日：1997-07-29

申请人： Koumei Hanaoka ,  Naoki Sakurai ,  Mutsuhiro Mori

发明人： Koumei Hanaoka ,  Naoki Sakurai ,  Mutsuhiro Mori

IPC分类号： H01L25/07 ,  H01L29/739 ,  H01L29/861 ,  H02J7/00 ,  H01L29/74 ,  H01L29/76 ,  H01L31/111 ,  H02H7/122

CPC分类号： H01L29/7395 ,  H01L25/072 ,  H01L2224/48091 ,  H01L29/861 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107 ,  H02J7/0029

摘要： An inverter apparatus constituted by one or more series connections of plural semiconductor devices each having a pair consisting of an insulated gate bipolar transistor, and a diode, both of which are in a reverse parallel connection with each other, wherein the resistivity of the base layer of the lowest impurity concentration in the diode is lower than that of the base layer of the lowest impurity concentration in the insulated gate bipolar transistor, and wherein a breakdown voltage of said insulated gate bipolar transistor at the time of switching from a conduction state to a blocking state is lower than a breakdown voltage of said insulated gate bipolar transistor and said diode at the time of the blocking state.

摘要翻译： 一种由多个半导体器件的一个或多个串联连接构成的逆变器装置，每个半导体器件具有由绝缘栅双极晶体管和二极管组成的对，它们都彼此反向并联连接，其中基极层的电阻率 二极管中最低杂质浓度的浓度低于绝缘栅双极型晶体管中最低杂质浓度的基底层，其中在从导通状态切换到所述绝缘栅双极型晶体管时，所述绝缘栅双极晶体管的击穿电压 阻塞状态低于阻塞状态时所述绝缘栅双极晶体管和所述二极管的击穿电压。

公开(公告)号：US6064080A

公开(公告)日：2000-05-16

申请号：US61150

申请日：1998-04-16

申请人： Hideki Nakamura

发明人： Hideki Nakamura

IPC分类号： H01L29/78 ,  H01L29/739 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7395

摘要： A direct-current power supply unit is provided for applying forward bias to a pn junction between an n emitter region and a p base region. A switch is provided between the direct-current power supply unit and a first metal electrode layer or a second metal electrode layer. A switch control circuit is connected to the switch. A gate control circuit is connected to the switch control circuit. Accordingly, ON voltage of an IGBT can be reduced while latch-up is avoided.

摘要翻译： 提供直流电源单元，用于向n发射极区域和p基极区域之间的pn结施加正向偏压。 在直流电源单元和第一金属电极层或第二金属电极层之间设置开关。 开关控制电路连接到开关。 门控制电路连接到开关控制电路。 因此，可以减少IGBT的导通电压，同时避免闩锁。

公开(公告)号：US6054728A

公开(公告)日：2000-04-25

申请号：US54946

申请日：1998-04-03

申请人： Yuichi Harada ,  Noriyuki Iwamuro ,  Tadayoshi Iwaana

发明人： Yuichi Harada ,  Noriyuki Iwamuro ,  Tadayoshi Iwaana

IPC分类号： H01L29/74 ,  H01L29/06 ,  H01L29/745 ,  H01L29/749 ,  H01L31/111

CPC分类号： H01L29/0692 ,  H01L29/7455 ,  H01L29/749

摘要： An insulated gate thyristor is provided which includes: a first-conductivity-type base layer, first and second second-conductivity-type base regions formed in the base layer, a first-conductivity-type source region formed in the first base region, a first-conductivity-type emitter region formed in the second base region, and a gate electrode layer formed on a gate insulating film over the first base region, first-conductivity-type base layer, and second base region, which are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region. The thyristor further includes a first main electrode that contacts with both the first base region and the first-conductivity-type source region, a second-conductivity-type emitter layer formed on the other surface of the first-conductivity-type base layer, a second main electrode that contacts with the second-conductivity-type emitter layer, a gate electrode connected to the gate electrode layer; and an insulating film covering entire surface areas of the second second-conductivity-type base region and the first-conductivity-type emitter region. In this insulated gate thyristor, an exposed surface portion of the first second-conductivity-type base region that is interposed between the first-conductivity-type base layer and the first-conductivity-type source region has a smaller width than an exposed surface portion of the second second-conductivity-type base region interposed between the first-conductivity-type base layer and the first-conductivity-type emitter region.

摘要翻译： 提供了一种绝缘栅晶闸管，其包括：第一导电型基极层，形成在基极层中的第一和第二第二导电型基极区域，形成在第一基极区域中的第一导电型源极区域， 形成在第二基极区域中的第一导电型发射极区域和形成在第一基极区域上的栅极绝缘膜上的栅极电极层，第一导电型基极层和第二基极区域， 导电型源极区域和第一导电型发射极区域。 晶闸管还包括与第一基极区域和第一导电型源极区域接触的第一主电极，形成在第一导电型基极层的另一个表面上的第二导电型发射极层， 与第二导电型发射极层接触的第二主电极，连接到栅电极层的栅电极; 以及覆盖所述第二第二导电型基极区域和所述第一导电型发射极区域的整个表面区域的绝缘膜。 在该绝缘栅极晶闸管中，介于第一导电型基极层和第一导电型源极区域之间的第一第二导电型基极区域的露出面部分的宽度比露出面部分 位于第一导电型基极层和第一导电型发射极区域之间的第二第二导电型基极区域。

公开(公告)号：US6037613A

公开(公告)日：2000-03-14

申请号：US28062

申请日：1998-02-23

申请人： Mitsuru Mariyama

发明人： Mitsuru Mariyama

IPC分类号： H01L29/74 ,  H01L29/747 ,  H01L31/111

CPC分类号： H01L31/1113

摘要： In a bidirectional photothyristor formed on a single N type silicon substrate, a distance between a P-gate diffusion region of one thyristor and an anode diffusion region of another thyristor opposed thereto is set to be 40 to 1,000 .mu.m, preferably, 70 to 600 .mu.m, thereby eliminating a malfunction caused by a noise due to a differentiation circuit which is composed of parasitic resistors and junction capacitances. In a field portion between the P-gate diffusion region and the anode diffusion region, an oxygen-doped semi-insulating film is formed via an SiO.sub.2 film, and an Al conductor is removed to form a field light receiving portion. Unlike a P-gate light receiving portion formed in the P-gate diffusion region, the field light receiving portion does not involve a junction capacitance. Therefore, a light sensitivity can be enhanced without lowering a dV/dt resistance.

摘要翻译： 在单个N型硅衬底上形成的双向光电晶闸管中，一个晶闸管的P栅极扩散区域和与其相对的另一个晶闸管的阳极扩散区域之间的距离设定为40〜1000μm，优选为70〜600μm 从而消除由由寄生电阻和结电容组成的微分电路引起的噪声的故障。 在P栅极扩散区域和阳极扩散区域之间的场部分中，通过SiO 2膜形成氧掺杂半绝缘膜，并且去除Al导体以形成场光接收部分。 不同于形成在P栅极扩散区域中的P栅极光接收部分，场光接收部分不涉及结电容。 因此，可以在不降低dV / dt电阻的情况下增强光灵敏度。

公开(公告)号：US6011280A

公开(公告)日：2000-01-04

申请号：US105610

申请日：1998-06-26

申请人： John Rothgeb Fruth ,  Stephen Paul Barlow ,  Jerral Alan Long ,  Michael Joseph Huemmer

发明人： John Rothgeb Fruth ,  Stephen Paul Barlow ,  Jerral Alan Long ,  Michael Joseph Huemmer

IPC分类号： H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7395 ,  H01L29/0615

摘要： A semiconductor power device (100) that includes active cells in an interior region of an epitaxial layer (16) on a semiconductor substrate (12), and an edge termination structure that surrounds the cells and separates the cells from the die edge (48). A polysilicon layer (26) overlies and is electrically insulated from the epitaxial layer (16), a gate metal field plate (36) contacts the polysilicon layer (26), and a portion of the polysilicon layer (26) forms a gate for each cell. Each of the active cells also has a collector/anode terminal formed by the substrate (12), an emitter/cathode terminal formed by a well (18), emitter diffusion (20) and emitter metal (22), and a base formed by the epitaxial layer (16). The edge termination structure includes a first well (34) of a first conductivity type underlying the polysilicon layer (26) and completely surrounding the active cells, a second well (30) of an opposite conductivity completely surrounding the first well (34), and metallization (42) contacting the second well (30). The first well (34) is part of a low-voltage ring (28) while the second well (30) is part of a high-voltage ring. The wells (30, 34) are preferably spaced relative to each other and to the device edge (48) to provide ballast resistance through the epitaxial layer (16), such that a breakdown will not be able to generate enough localized current to damage or destroy the device (100) when a reverse power pulse is experienced.

摘要翻译： 一种半导体功率器件（100），其包括在半导体衬底（12）上的外延层（16）的内部区域中的有源电池，以及围绕所述电池并将所述电池与所述冲模边缘（48）分离的边缘终端结构， 。 多晶硅层（26）覆盖并与外延层（16）电绝缘，栅极金属场板（36）接触多晶硅层（26），并且多晶硅层（26）的一部分形成每个栅极 细胞。 每个活性电池还具有由衬底（12）形成的集电极/阳极端子，由阱（18），发射极扩散（20）和发射极金属（22）形成的发射极/阴极端子和由 外延层（16）。 边缘终端结构包括在多晶硅层（26）下面并完全围绕活性细胞的第一导电类型的第一阱（34），完全围绕第一阱（34）的相反电导率的第二阱（30），以及 金属化（42）与第二阱（30）接触。 第一阱（34）是低压环（28）的一部分，而第二阱（30）是高压环的一部分。 阱（30,34）优选地相对于彼此和器件边缘（48）间隔开，以通过外延层（16）提供镇流电阻，使得击穿将不能产生足够的局部电流来损坏或 当发生反向功率脉冲时，破坏设备（100）。

公开(公告)号：US5990501A

公开(公告)日：1999-11-23

申请号：US866158

申请日：1997-05-30

申请人： Michiaki Hiyoshi ,  Kazunobu Nishitani

发明人： Michiaki Hiyoshi ,  Kazunobu Nishitani

IPC分类号： H01L27/00 ,  H01L21/52 ,  H01L23/051 ,  H01L23/48 ,  H01L25/07 ,  H01L25/18 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L23/051 ,  H01L24/72 ,  H01L2924/01004 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A multichip press-contact type semiconductor device including a plurality of semiconductor chips, a plurality of heat buffer plates, a conductive metal sheet, and first and second press-contact electrode plates. The heat buffer plates are disposed to correspond to the plurality of semiconductor chips. The conductive metal sheet is located on the plurality of heat buffer plates and substantially decreases the parasitic inductance by causing a short-circuit in electrode wiring connecting the semiconductor chips. The first press-contact electrode plate is located on the conductive metal sheet, and has column protrusions corresponding to the semiconductor chips on the surface facing the semiconductor chips. The second press-contact electrode plate is located on the side of the rear surface of the semiconductor chips. The first and second press-contact electrode plates hold therebetween the conductive metal sheet, the heat buffer plates, and the semiconductor chips, piled on each other.

摘要翻译： 包括多个半导体芯片，多个热缓冲板，导电金属片以及第一和第二压接电极板的多芯片压接触型半导体器件。 热缓冲板被设置成对应于多个半导体芯片。 导电金属片位于多个加热缓冲板上，通过在连接半导体芯片的电极布线中引起短路而大大降低寄生电感。 第一压触电极板位于导电金属片上，并且在面向半导体芯片的表面上具有对应于半导体芯片的列突起。 第二压接电极板位于半导体芯片的背面侧。 第一和第二压接电极板之间夹持导电金属片，热缓冲板和半导体芯片，彼此堆叠。