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    FRACTIONAL-N JITTER ATTENUATOR
    73.
    发明申请
    FRACTIONAL-N JITTER ATTENUATOR 有权

    公开(公告)号：US20180138915A1

    公开(公告)日：2018-05-17

    申请号：US15612982

    申请日：2017-06-02

    申请人： Perceptia Devices, Inc.

    发明人： Julian Jenkins ,  André Grouwstra

    IPC分类号： H03L7/14 ,  H03L7/091 ,  H03L7/197

    CPC分类号： H03L7/14 ,  H03L7/0802 ,  H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/181 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

    摘要： A phase-locked loop (PLL) has a primary loop (with a reference clock) and a secondary loop (with a stable reference clock). The secondary loop may include a fractional-N PLL, and may include a secondary loop filter, oscillator, output clock counter, and phase predictor using a rational secondary frequency control word (FCW). The primary loop has a register sampling the oscillator phase from the counter, and a phase predictor which uses a primary fractional-N FCW to calculate a predicted phase as an integer number. The primary loop forwards the integer difference between the sampled phase and the predicted phase to a primary loop filter, which outputs the secondary FCW. The primary loop filter has a much lower bandwidth than the secondary loop filter. The PLL may have multiple primary loops, with a hitless switching function. A primary loop may have sleep mode. The PLL may also provide an oscillator sleep function.

    Delay locked loop
    74.
    发明授权
    Delay locked loop 有权

    公开(公告)号：US09917590B2

    公开(公告)日：2018-03-13

    申请号：US15172115

    申请日：2016-06-02

    申请人： Marvell World Trade Ltd.

    发明人： Tao Zhang ,  Xuemei Liu ,  Hui Wang

    IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40 ,  H03L7/08 ,  H03L7/081 ,  H03L7/091 ,  H03K5/06

    CPC分类号： H03L7/0807 ,  H03K5/06 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0037 ,  H04L7/0337

    摘要： A programmable delay line comprises a delay stage responsive to an analog control signal and responsive to one or more digital control signals. The delay stage generates an output signal that is delayed relative to an input signal by a delay amount. The delay amount controlled by a value of the analog control signal and one or more values of the digital control signals. A method for controlling a delay locked loop circuit comprises providing, to a programmable delay line of the delay locked loop circuit, a one or more digital signals, and providing, to the programmable delay line, an analog signal. A first portion of a delay produced by the programmable delay line corresponds to values of the one or more digital signals. A second portion of the delay produced by the programmable delay line corresponds to a value of the analog signal.

    Clock Alignment Scheme for Data Macros of DDR PHY
    75.
    发明申请
    Clock Alignment Scheme for Data Macros of DDR PHY 有权

    公开(公告)号：US20180006656A1

    公开(公告)日：2018-01-04

    申请号：US15707205

    申请日：2017-09-18

    申请人： Invecas, Inc.

    发明人： Narasimhan Vasudevan ,  Venkata N.S.N. Rao ,  Prasad Chalasani

    IPC分类号： H03L7/081 ,  H03L7/083 ,  G11C11/4063 ,  H03L7/091 ,  G11C7/22

    CPC分类号： H03L7/0818 ,  G11C7/222 ,  G11C11/4063 ,  G11C11/4076 ,  H03L7/0812 ,  H03L7/083 ,  H03L7/085 ,  H03L7/089 ,  H03L7/091

    摘要： A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) for generating at least one bias voltage and at least one slave delay locked loop (“SDLL”). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.

    PHASE-LOCKED LOOPS WITH ELECTRICAL OVERSTRESS PROTECTION CIRCUITRY
    76.
    发明申请
    PHASE-LOCKED LOOPS WITH ELECTRICAL OVERSTRESS PROTECTION CIRCUITRY 有权

    公开(公告)号：US20170366190A1

    公开(公告)日：2017-12-21

    申请号：US15187534

    申请日：2016-06-20

    申请人： Altera Corporation

    发明人： Chee Seng Leong

    IPC分类号： H03L7/08 ,  H03L7/089 ,  H03L7/091 ,  H03L7/099

    CPC分类号： H03L7/0807 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/0995 ,  H03L7/14

    摘要： An integrated circuit with a phase-locked loop (PLL) is provided. The PLL may include a phase frequency detector, a charge pump, a source follower circuit, a variable oscillator, a frequency divider, and a control block. The phase frequency detector may be configured to align or lock a feedback clock signal to a reference clock signal. The control block includes clock loss detection circuits that are used to determine whether the reference clock signal or the feedback clock signal has stopped toggling. In response to detecting a clock loss event for either the reference or the feedback clock signal, the control block may disable the phase frequency detector to place the charge pump in a tristate mode and may apply a predetermined bias voltage to the source follower circuit to help minimize electrical overstress.

    Phase detector
    77.
    发明授权
    Phase detector 有权

    公开(公告)号：US09831861B2

    公开(公告)日：2017-11-28

    申请号：US14842591

    申请日：2015-09-01

    申请人： FUJITSU LIMITED

    发明人： Nikola Nedovic

    IPC分类号： H03L7/08 ,  H03K5/1534 ,  H03L7/081 ,  H03L7/091

    CPC分类号： H03K5/1534 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/091

    摘要： A phase detection circuit includes a first sample circuit, a second sample circuit, and a third sample circuit. The first sample circuit may be configured to sample a first signal based on a first phase of a second signal to generate a first sample of the first signal and to output the first sample. The second sample circuit may be configured to sample the first signal based on a second phase of the second signal to generate a second sample of the first signal and to output second sample. The third sample circuit coupled to the first sample circuit and to the second sample circuit. The third sample circuit may be configured to sample the first sample based on a change of the second sample to generate a third sample and to output the third sample.

    DELAY LOCKED LOOP INCLUDING A DELAY CODE GENERATOR
    78.
    发明申请
    DELAY LOCKED LOOP INCLUDING A DELAY CODE GENERATOR 审中-公开

    公开(公告)号：US20170338825A1

    公开(公告)日：2017-11-23

    申请号：US15599191

    申请日：2017-05-18

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Hoon Lee ,  Donghun Lee ,  Jaewon Lee

    IPC分类号： H03L7/081 ,  H03L7/091 ,  H03K19/20

    CPC分类号： H03L7/0818 ,  H03K5/131 ,  H03K19/20 ,  H03K2005/00234 ,  H03L7/0816 ,  H03L7/085 ,  H03L7/091 ,  H03L7/10

    摘要： A delay locked loop includes a delay line, a delay circuit, a phase detector, a delay code generator, and a delay controller. The delay line may delay an input clock signal in units of unit delay in response to a delay control code to generate an output clock signal. The delay circuit may delay the output clock signal to generate a delay clock signal. The phase detector may compare the input clock signal and the delay clock signal to generate a phase detection signal. The delay code generator may compare the input clock signal and the delay clock signal to detect a phase difference therebetween, and generate a delay code using the phase difference. The delay controller may generate the delay control code using the delay code and the phase detection signal.

    PLL circuit and operation method
    80.
    发明授权
    PLL circuit and operation method 有权

    公开(公告)号：US09819351B2

    公开(公告)日：2017-11-14

    申请号：US15431843

    申请日：2017-02-14

    申请人： Renesas Electronics Corporation

    发明人： Yasuyuki Hiraku

    IPC分类号： H03L7/06 ,  H03L7/095 ,  H03L7/183 ,  H03L7/089 ,  H03L7/091

    CPC分类号： H03L7/095 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/093 ,  H03L7/107 ,  H03L7/1075 ,  H03L7/18 ,  H03L7/183 ,  H03L7/185

    摘要： A PLL circuit having a desired performance is provided. A PLL circuit (100) includes a phase comparator (11) that detects a phase difference; a voltage control oscillator (12) that generates a signal to be returned to the phase comparator (11); and a loop filter (10) that is disposed between the phase comparator (11) and the voltage control oscillator (12) and includes an adder (50) that adds outputs from a proportional path (20), a first integral path (40), and a second integral path (30). The second integral path (30) and the first integral path (40) each include a cumulative adder, a ΔΣ modulator, and an RC filter. The lock detector (36) detects a lock state, controls a gain of the first cumulative adder (42) and a bandwidth of the first RC filter (45), and switches an input to a second ΔΣ modulator (33) to a fixed value.